Abstract
Lightweight cryptography plays an essential role for emerging authentication-based pervasive computing applications in resource-constrained environments. In this paper, we have proposed resource-efficient and high-performance VLSI architectures for PRESENT block cipher algorithm for the two key lengths 80-bit and 128-bit, namely PRESET-80 and PRESENT-128. The FPGA implementations of these architectures have been done on LUT-6 technology based Xilinx Virtex-5 XC5VFX70T-1-FF1136 FPGA device. These architectures have a latency of 33 clock cycles, run at a maximum clock frequency of 306.84 MHz and provide throughput of 595.08 Mbps. They have been compared with the two different established architectures. It has been observed that the PRESENT-80 architecture consumes 20.3% lesser FPGA slices and there is a gain of 25.4% in throughput. Similarly, the PRESENT-128 architecture requires 20.7% lesser FPGA slices alongwith a reduction in the latency by 27.7% and an overall increase of throughput by 69.1%.
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Pandey, J.G., Goel, T., Karmakar, A. (2017). An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_27
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DOI: https://doi.org/10.1007/978-981-10-7470-7_27
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