Abstract
Full adders are the building blocks of nearly all the VLSI applications—be it digital signal processing or image and video processing. In this paper, an 8-bit Carry Look-ahead Adder is implemented and compared using two different types of designs—a conventional Complementary Metal-Oxide Semiconductor (CMOS) logic and an Efficient Charge Recovery Logic (ECRL). These adders are designed and simulated using Tanner Tools v15.23 with 180 nm technology. Performance parameters like power consumption and propagation delay are compared by varying input supply and operating frequency for the two different circuits. The comparison shows that an 8-bit CLA design using ECRL Adiabatic logic is better than an 8-bit CLA design using CMOS logic in terms of power consumption, transistor count, and power delay product (PDP).
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Ameta, S., Maurya, V., Hussain, A., Agrawal, N. (2018). Design and Analysis of 8-Bit Carry Look-Ahead Adder Using CMOS and ECRL Technology. In: Perez, G., Tiwari, S., Trivedi, M., Mishra, K. (eds) Ambient Communications and Computer Systems. Advances in Intelligent Systems and Computing, vol 696. Springer, Singapore. https://doi.org/10.1007/978-981-10-7386-1_5
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DOI: https://doi.org/10.1007/978-981-10-7386-1_5
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