Skip to main content

A Dual-Coding Technique to Reduce Dynamic Power Dissipation in Deep Submicron (DSM) Technology

  • Conference paper
  • First Online:
Ambient Communications and Computer Systems

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 696))

  • 1207 Accesses

Abstract

In a typical bus system, 10% of the power dissipation is static or leakage and 90% is dynamic power. Hence, dynamic power dissipation reduction is main objective of our current research work. In our current research work, power dissipation is reduced in deep submicron (DSM) technology. It has been found that 75% of dynamic power dissipation is due to coupling transitions, whereas only 25% is due to self-transitions. This paper develops a novel technique, dual coding algorithm, in which inter-wire capacitance considers sufficiently and reduces the average power dissipation due to coupling transition approximately up to 50–66.66% with an additional area penalty. The effectiveness of coding method has been tested using MATLAB. Transmission results are tested on bus of system on chip which is simulated on Xilinx and implemented on FPGA.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 259.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 329.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Paul P. Sotiriadis and Anantha P. Chandrakasan, “A Bus Energy Model for Deep Submicron Technology,” IEEE transactions on VLSI systems, vol. 10, no. 3, June 2002.

    Google Scholar 

  2. J.V.R. Ravindra, Navya Chittarvu & M.B. Srinivas, “Energy Efficient Spatial Coding Technique for Low Power VLSI Applications,” IEEE, 27–29 Dec. 2006.

    Google Scholar 

  3. Ge Chen, Steven Duvall & Saeid Nooshabadi, “Analysis and Design of Memoryless Interconnect Encoding Scheme,” IEEE 2009.

    Google Scholar 

  4. J.V.R. Ravindra, K.S. Sainarayanan and M.B. Srinivas, “A Novel Bus Coding Technique for Low Power Data Transmission,” 2007.

    Google Scholar 

  5. Mircea R. Stan and Wayne P. Burleson, “Bus Invert Coding for Low Power I/O,” IEEE Transactions on Very Large Scale Integration System, Vol. 3, No.1, March 1995.

    Google Scholar 

  6. Deepika Agarwal, G. Nagendra Babu, B. K. Kaushik & S. K. Manhas, “Reduction of Crosstalk in RC Modeled Interconnects with Low Power Encoder,” Indian Institute of Technology, Roorkee, 2011 IEEE.

    Google Scholar 

  7. Ojashri Sharma, Aakash Saini, Sandeep Saini & Abhishek Sharma, “A Quadro Coding Technique to Reduce Self Transitions in VLSI Interconnects,” IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)2016.

    Google Scholar 

  8. A. Sathish, Dr. M. Madhavi Latha & Dr. K. Lal Kishore, “Efficient Crosstalk Reduction Technique for Data Bus,” International Journal of Computer Applications, Volume 28, No. 11, August 2011.

    Google Scholar 

  9. C. Raghunandan, K.S. Sainarayanan & M.B. Srinivas, “Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN),” International Institute of Information Technology (IIIT), Hyderabad, India 2007 IEEE.

    Google Scholar 

  10. Xin Zhao, Xi Tian, ShaoShi Yan & Yongfeng Guan, “A novel low power bus coding technique for nanometer technology,” IEEE, 2007.

    Google Scholar 

  11. N. Vithya Lakshmi & M. Rajaram, “An Octo Coding Technique to Reduce Energy Transition in Low Power VLSI Circuits,” IJRET: International Journal of Research in Engineering and Technology, Volume: 02, Issue: 11, Nov 2013.

    Google Scholar 

  12. K.S. Sainarayanan, J.V.R. Ravindra, C. Raghunandan and M.B. Srinivas, “Coupling Aware Energy-Efficient Data Scrambling on Memory-Processor Interfaces,” Second International Conference on Industrial and Information Systems, ICIIS 2007, 8–11 August 2007, Sri Lanka.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Tanu Verma .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Verma, T. (2018). A Dual-Coding Technique to Reduce Dynamic Power Dissipation in Deep Submicron (DSM) Technology. In: Perez, G., Tiwari, S., Trivedi, M., Mishra, K. (eds) Ambient Communications and Computer Systems. Advances in Intelligent Systems and Computing, vol 696. Springer, Singapore. https://doi.org/10.1007/978-981-10-7386-1_2

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-7386-1_2

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7385-4

  • Online ISBN: 978-981-10-7386-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics