Abstract
The crosstalk problems of interconnects are one of the main problems in DSM of switching network high-speed buses. To avoid the problem of crosstalk, we provided the crosstalk avoidance codes (CACs) to avoid the crosstalk problem. In this chapter, we will traverse and then produce FTC that should not have opposed directions of transitions, any direction of n number of neighboring wires in the channel. In this, we proposed a new method called a low-power algorithm for sequential and parallel bit stuffing. The low-power algorithm is for sequential and parallel bit stuffing by just inserting inverters (NOT gate) by avoiding the opposite transitions in the channel. We show the results of both algorithms (serial and parallel) of bit-stuffing (bus encoding) simulations and bit-removing (bus decoding) simulations using Verilog HDLs and synthesis and implement in FPGA. Compared to sequential bit stuffing, algorithms are somewhat more rapidly fast than the bit stuffing. And also we are finding the coding rate of both algorithms. The algorithms achieved not only higher coding rates but also lower power. Finally, we can extend the bit stuffing encoding system for generating forbidden transition codes (FTC) that avoid the two transition patterns, “01→10” and “10→01”, on any four adjacent wires.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
P. P. Sotiriadis, “Interconnect modeling and optimization in deep submicron technologies,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, USA, 2002.
B. Victor and K. Keutzer, “Bus encoding to prevent crosstalk delay,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, SanJose, CA, USA, Nov. 4–8, 2001, pp. 57–63.
M. Mutyam, “Preventing crosstalk delay using Fibonacci representation,” in Proc. 17th Int. Conf. VLSI Design, Mumbai, India, Jan. 5–9, 2004, pp. 685–688.
B. E. Moision, A. Orlitsky, and P. H. Siegel, “On codes that avoid specified difference,” IEEE Trans. Inf. Theory, vol. 47, no. 1, pp. 433–442, Jan. 2001.
C. Duan, C. Zhu, and S. P. Khatri, “Forbidden transition free crosstalk avoidance CODEC design,” in Proc. 45th Annu. Design Autom. Conf., Anaheim, CA, USA, Jun. 8–13, 2008, pp. 986–991.
X. Wu, Z. Yan, and Y. Xie, “Two-dimensional crosstalk avoidance codes,” in Proc. IEEE Workshop Signal Process. Syst., Washington, DC, USA, Oct. 8–10, 2008, pp. 106–111.
S. R. Sridhara and N. R. Shanbhag, “Coding for system-on-chip networks: A unified framework,” IEEE Trans. Very Large Scale Integr. Syst., vol. 13, no. 6, pp. 655–667, Jun. 2005.
W.-W. Hsieh, P.-Y. Chen, C.-Y. Wang, and T.-T. Hwang, “A busen coding scheme for crosstalk elimination in high-performance processor design,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 12, pp. 2222–2227, Dec. 2007.
C.-S. Chang, J. Cheng, T.-K. Huang, and D.-S. Lee, “Explicit constructions of memoryless crosstalk avoidance codes via Ctransform,” IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 9, pp. 2030–2033, Sep. 2014.
L. L. Peterson and B. S. Davie, Computer Networks: A Systems Approach, 4th ed. San Francisco, CA, USA: Morgan Kaufmann, 2007.
R. M. Roth, P. H. Siegel, and J. K. Wolf, “Efficient coding schemes for the hard-square constraint,” IEEE Trans. Inf. Theory, vol. 47, no. 9, pp. 1166–1176, Mar. 2001.
S. Halevy, J. Chen, R. M. Roth, P. H. Siegel, and J. K. Wolf, “Improved bit-stuffing bounds on two-dimensional constraints,” IEEE Trans. Inf. Theory, vol. 50, no. 5, pp. 824–838, May 2004.
S. Aviran, P. H. Siegel, and J. K. Wolf, “An improvement to the bit stuffing algorithm,” IEEE Trans. Inf. Theory, vol. 51, no. 8, pp. 2885–2891, Aug. 2005.
Cheng-Shang Chang, Jay Cheng, Tien-Ke Huang, Xuan-Chao Huang, Duan-Shin Lee and Chao-Yi Chen,”Bit-Stuffing Algorithms for Crosstalk Avoidance in High-Speed Switching” IEEE Transactions On Computers, Vol. 64, No. 12, December 2015.
J. D. Z. Ma and L. He, “Formulae and applications of interconnect estimation considering shield insertion and net ordering,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, San Jose, CA, USA, Nov. 4–8, 2001, pp. 327–332.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Obulesu, B., Sudhakara Rao, P. (2018). Design and Implementation of Low-Power Memory-Less Crosstalk Avoidance Codes Using Bit-Stuffing Algorithms. In: Anguera, J., Satapathy, S., Bhateja, V., Sunitha, K. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 471. Springer, Singapore. https://doi.org/10.1007/978-981-10-7329-8_10
Download citation
DOI: https://doi.org/10.1007/978-981-10-7329-8_10
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7328-1
Online ISBN: 978-981-10-7329-8
eBook Packages: EngineeringEngineering (R0)