A 79 GHz CMOS LNA with Adaptive Biasing

Abstract

This paper proposes a high-gain and low-noise 79 GHz CMOS LNA using an adaptive biasing circuit for radar application. To achieve high gain, an LNA with a two-stage differential cascode (common source and common gate) topology is used. In the first stage, source degeneration inductors are used for both input and noise matching. Second stage of LNA consists of adaptive biasing circuit which automatically controls gain with respect to the received power. Adaptive biasing circuit is a three-stage common source amplifier to decrease output voltage as the input power increases. It provides a wide dynamic range and covers the entire detection range. The proposed design is analyzed in 180 nm CMOS technology using ADS tool. The designed LNA provides a voltage gain of more than 22 dB at 79 GHz with the input reflection coefficient (S11) of −5.7 dB, reverse isolation (S12) of −20 dB, forward transmission coefficient (S21) of −18 dB, and output reflection coefficient (S22) of −1.5 dB with the noise figure of less than 5 dB. The second stage of LNA with adaptive biasing circuit lowers the gain as the received power increases which typically gives an AC gain of 0.9 dB at 79 GHz.