Adiabatic Techniques for Energy-Efficient Barrel Shifter Design

Abstract

One of the efficient ways to design a low power consumption logic style is the adiabatic logic circuits. This is far better than conventional CMOS logic in terms of power consumptions, delay, and efficiency. This paper explains the design of a 4-bit Barrel shifter using two different adiabatic logics, namely positive feedback adiabatic logic (PFAL) and pass transistor adiabatic logic (PAL). A Barrel shifter is effectively used in arithmetic and logical operations. PFAL utilizes positive feedback technique. The structure contains an adiabatic amplifier. The latch of PFAL is made by two PMOS and two NMOS transistors that avoid logic level degradation at output nodes. Energy recovery in the recovery phase of the clock supply results in a reduction in the power consumption. However, it is not suitable to the application where the delay is critical as the PFAL suffers from large switching time. PAL is a dual-rail adiabatic logic with low gate complexity. It also operates in two-phase power clock. With the use of PFAL and PAL logics, we are going to design 4-bit Barrel shifter. The circuit simulation is performed on Cadence Virtuoso using 180-nm CMOS technology. The parameters such as delay and power dissipation are calculated. From the simulation results obtained, it shows PAL adiabatic logic is more efficient than PFAL adiabatic logic because of reduction of non-adiabatic losses in PAL.