Abstract
Objective/Background: Multi-stage CMOS OTAs have been used in vast areas like micro-sensor nodes, Bio-medical applications. In this paper, a three-stage CMOS OTA has been designed in 180 nm technology, which is suitable for low-power applications requiring high driving capability. Methods/Analysis: When both low-power and low-voltage operation are the goals, MOS transistors operating in subthreshold regions are used. So, in this work, all the transistors of the amplifier operate in subthreshold region. Reversed Nested Miller Compensation (RNMC) technique is used for stabilizing the amplifier. A slew-rate enhancer (SRE) is used to enhance the slew-rate of the amplifier after compensation. Findings: Powered with 1-V supply, the proposed OTA can drive loads up to 450 pF with phasemargin for this maximum load as 45°. The maximum gain achieved is 120 dB for low frequencies. Power dissipation is obtained as 275.39 nW for low capacitive loads (200 pF). Cadence Virtuoso-64 tool is used for simulations. Conclusion/Improvements: The problem with slew-rate at higher frequencies has been found to be not at the final stage but at the first stage and is resolved using the SRE circuit for a stabilized three-stage OTA. The stabilized and slew enhanced amplifier can drive up to 450 pF load with around 4 µW power dissipation.
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Paturi, R.K.M., Manikandan, P. (2018). Design of Multi-stage CMOS OTA for Low-Power and High Driving Capability. In: Li, J., Sankar, A., Beulet, P. (eds) VLSI Design: Circuits, Systems and Applications . Lecture Notes in Electrical Engineering, vol 469. Springer, Singapore. https://doi.org/10.1007/978-981-10-7251-2_27
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DOI: https://doi.org/10.1007/978-981-10-7251-2_27
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