Abstract
In this paper, a high-performance domino logic style with reduced delay and less delay variability under process parameter variations is presented. An improved control methodology with delayed enabling of the keeper circuit using the clock signal is proposed. This makes the keeper to be idle during the start of the evaluation phase and reduces the contention. It also helps in increasing the speed performance of the circuit. Furthermore, the reduced loop gain due to the modified keeper circuit lessens the delay variations. The proposed keeper control circuits demonstrate delay reduction of 46% compared to the conventional domino logic circuit. The statistical variations of the process parameters using Monte Carlo analysis demonstrate the reduced delay variations to the tune of 48% for 100 runs. The circuits are simulated using Cadence Virtuoso® employing 180 nm technology node libraries.
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Anita Angeline, A., Kanchana Bhaaskaran, V.S. (2018). High Performance Domino Logic Circuit Design by Contention Reduction. In: Li, J., Sankar, A., Beulet, P. (eds) VLSI Design: Circuits, Systems and Applications . Lecture Notes in Electrical Engineering, vol 469. Springer, Singapore. https://doi.org/10.1007/978-981-10-7251-2_18
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DOI: https://doi.org/10.1007/978-981-10-7251-2_18
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