A Novel Adiabatic Logic for Low Power VLSI Circuit Design and Power Optimization Using FinFET

Abstract

In this article, a novel low power adiabatic circuit, namely the modified complementary pass transistor logic (MCPAL) powered by a four phase power clock supply, is proposed. The important features of the proposed logic are its low leakage power, glitch free output, and lower switching noise compared to the counterpart circuits found in the literature. Efficiency of the proposed adiabatic logic is validated by comparing with the basic inverter circuits designed using 2N2P, 2N-2N2P, PFAL, CPAL, and DCPAL type of adiabatic logic circuits. Secondly, the utilization of self-aligned double gate FinFETs in the design of MCPAL is also studied, with the use of an inverter and 512 stages of cascaded inverters implemented using 32 nm FinFET and 32 nm lower technology MOSFET by employing their corresponding BSIM model files. The circuits are designed and simulated in Cadence Virtuoso^® tool environment through an operating frequency range from KHz to GHz.