Abstract
In this proposal, we explained about 5T embedded DRAM cell which is designed based on Schmitt trigger concept. The proposed design is mainly useful for low-power, small-size applications with greatly reduced cost prize. Also, Schmitt trigger-based bit cells incorporate a built-in feedback mechanism which will be greatly useful for further nanoscaled devices. It was simulated using 45-nm CMOS process technology, and the obtained results prove that the design achieves increased read and write static noise margin (SNM) when compared with conventional 6T and 10T bit cells when powered with 0.9 V. The design also possesses lowest leakage power dissipation comparatively.
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Snigdha Chandrika, V., Maria Dominic Savio, M. (2018). Designing 5T Embedded DRAM Cell for Ultra-Low-Power Low-Voltage Applications Based on Schmitt Trigger. In: Li, J., Sankar, A., Beulet, P. (eds) VLSI Design: Circuits, Systems and Applications . Lecture Notes in Electrical Engineering, vol 469. Springer, Singapore. https://doi.org/10.1007/978-981-10-7251-2_11
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DOI: https://doi.org/10.1007/978-981-10-7251-2_11
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