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Design and Analysis of a CMOS 180-nm Fractional-N Frequency Synthesizer

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 466))

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Abstract

The design of a Fractional-N Frequency Synthesizer in CMOS 180-nm that operates in GHz range is discussed. The proposed frequency synthesizer is realized using a phase-locked loop with phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and a programmable frequency divider. The characteristics of the PFD are extremely linear as one of the input frequencies is modulated. The frequency divider deigned is a programmable one as it can generate noninteger division ratios unlike an integer PLL.

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Correspondence to P. Parvathy .

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© 2018 Springer Nature Singapore Pte Ltd.

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Parvathy, P., Saraswathi, N. (2018). Design and Analysis of a CMOS 180-nm Fractional-N Frequency Synthesizer. In: Labbé, C., Chakrabarti, S., Raina, G., Bindu, B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore. https://doi.org/10.1007/978-981-10-7191-1_5

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  • DOI: https://doi.org/10.1007/978-981-10-7191-1_5

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7190-4

  • Online ISBN: 978-981-10-7191-1

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