Abstract
Background: Memories occupy the majority of chip area, and the response time for any system depends on its memory too. So, SRAMs are critical to the speed of processor operations and thus need to be rigorously optimized. The optimizations have to be in such a way that the constraints of better performance as well as reliability are met. Methods/Statistical analysis: The proposed bit cell is compared with conventional 6T bit cell for access time, read stability, on-current, and off-current, and the suitable sense amplifiers and decoder are analyzed. Findings: The proposed architecture for SRAM design meets the criteria of faster access time and read stability as compared to the conventional 6T SRAM. Write 1 operation achieves a rise of 16%, while write 0 and read 1 are better than 6T by 70 and 90%, respectively. The design was implemented on 28 nm FD-SOI platform. Application/Improvements: The proposed design has the better read stability as compared to the conventional 6T SRAM bit cell design.
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Acknowledgements
We thank our team at STMicroelectronics for the opportunity and support during our work on the memory. We would also like to thank Mr. Bedanta Choudhury, Mr. Manish Arora, and Mr. Prashant Jain for their helpful guidance.
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Lourts Deepak, A., Gandotra, M., Yadav, S., Gandhi, H., Umadevi, S. (2018). 28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture. In: Labbé, C., Chakrabarti, S., Raina, G., Bindu, B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore. https://doi.org/10.1007/978-981-10-7191-1_18
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DOI: https://doi.org/10.1007/978-981-10-7191-1_18
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