A Modified GDI-Based Low-Power and High Read Stability 8-T SRAM Memory with CNTFET Technology

Abstract

Background/Objectives: There is an enhancement in the short channel effects and leakage current as the devices are scaled down. Hence, it is almost impossible to design SRAM with high storage capacity and lower power dissipation using the current technology. To achieve higher efficiency and to decrease the power dissipation, a migration to Carbon Nanotube Field Effect Transistor (CNTFET) technology is imperative. GDI technique is one of the low-power methodologies employed to enhance the efficiency of the logic circuit. But to further reduce the leakage power of the circuits, the modified GDI (m-GDI) technique is used. Methods/Statistical analysis: The proposed work aims at designing an 8-T SRAM cell for high read stability and low power dissipation, using the modified GDI cell (m-GDI) technique based on conventional GDI cell. The simulation is done using Cadence Virtuoso with a supply voltage of 900 mV. Stability analysis is also performed for the SRAM cell. Findings: m-GDI technique solves the problem of voltage degradation in GDI technique. An 8-T SRAM cell with low power and high read stability is implemented. CNTs with chirality vector (13, 0) are found to be a good choice for low-power and stable SRAM cell. Improvements/Applications: CNTFET with m-GDI-based memories with their low power and high read stability has the potential to replace the current technology, if the shortcomings in the implementation are conquered.