Abstract
Objectives: Faults in the random access memories have been a major cause of concern with increase in technology. Built-in self-test technique is generally used to detect the faults in memories, and built-in self-repair (BISR) technique has been widely used to repair the memories. This paper discusses the configurable BISR (CBISR) technique for repairing random access memories with variable sizes and redundancy structures. An effective redundancy analysis method is proposed to replace defective cells. Methods/Statistical analysis: In this paper, stuck-at faults basically the stuck-at 1 (SA1) fault are detected and a built-in self-repair (BISR) architecture for the random access memories mainly for SRAM is designed and implemented on Cadence Virtuoso-64 tool in 180 nm technology. Findings: An efficient method to test and repair the stuck-at faults by redundancy. The redundancy method repairs the faulty memory with a fault-free one using a redirection mechanism. Application/Improvements: Better coverage of stuck-at faults and repair of the faulty memory.
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Authors would like to thank the anonymous reviewers for their comments in improving the paper and also extend our gratitude to VIT University, Chennai for their support.
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Patnaik, S., Ravi, V. (2018). A Built-in Self-Repair Architecture for Random Access Memories. In: Labbé, C., Chakrabarti, S., Raina, G., Bindu, B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore. https://doi.org/10.1007/978-981-10-7191-1_13
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DOI: https://doi.org/10.1007/978-981-10-7191-1_13
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