Skip to main content
SpringerLink
Log in
Book cover

Advanced Multicore Systems-On-Chip pp 225–244Cite as

Power Optimization Techniques for Multicore SoCs

  • Chapter
  • First Online:

Abstract

Power dissipation continues to be a primary design constraint in single and multicore systems. Increasing power consumption not only results in increasing energy costs, but also results in high die temperatures that affect chip reliability, performance, and packaging cost. Energy conservation has been largely considered in the hardware design in general and also in embedded multicore systems’ components, such as CPUs, disks, displays, memories, and so on. Significant additional power savings can be also achieved by incorporating low-power methods into the design of network protocols used for data communication (audio, video, etc.). This chapter investigates in details power reduction techniques at components and the network protocol levels.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   99.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   179.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. R. Kravets, P. Krishnan, Application driven power management for mobile communication Springer Science. Wirel. Netw. 6(4), 263–277 (2000)

    Article  MATH  Google Scholar 

  2. J. Lorch, Modeling the effect of different processor cycling techniques on power consumption, Performance evaluation group technical note 179, in ATG Integrated Sys, Apple Computer, 1995

    Google Scholar 

  3. T. Martin, Balancing batteries, power and performance: system issues in CPU speed-setting for mobile computing, Ph.D. Dissertation, Carnegie Mellon University, Department of Electrical and Computer Engineering, Aug, 1999

    Google Scholar 

  4. G.F. Welch, A survey of power management techniques in mobile computing operating systems. ACM SIGOPS Oper. Syst. Rev. 29(4), 47–56 (1995)

    Google Scholar 

  5. J.M. Rulnick, N. Bambos, Mobile power management for maximum battery life in wireless communication networks, in Proceedings of IEEE INFOCOM 96, 1996

    Google Scholar 

  6. F.N. Najm, A survey of power estimation techniques in VLSI circuits. IEEE Trans. VLSI Syst. 2(4), 44–55 (1994)

    Article  Google Scholar 

  7. M. Pedram, Power minimization in IC design: principles and applications. ACM Trans. Des. Autom. Electron. Syst. 1(1), 3–6 (1996)

    Article  Google Scholar 

  8. S. Borkar, Design challenges of technology scaling. IEEE Micro. 19(4), 23–29 (1999)

    Article  Google Scholar 

  9. Semiconductor industry association: the national technology roadmap for semiconductors: technology needs, Sematche Inc. (Austin, USA, 1997), http://www.sematech.org

  10. Y. Ye. S. Borkar, V. De. A new technique for standby leakage reduction in high-performance circuits, in Symposium on VLSI Circuits, Honolulu, Hawaii, 40–41 1998

    Google Scholar 

  11. L. Benini, G. de Micheli, System-level power optimization: techniques and tools, in Proceedings Intéz Symposium Low-Power Electronics Design, San Diego, CA, 288–293 1999

    Google Scholar 

  12. L. Benini, G. de Micheli, E. Macii, Designing low-power circuits: practical recipes. IEEE Circuits Syst. Mag. 1, 6–25 (2001)

    Article  Google Scholar 

  13. A. Ben Abdallah, S. Kawata, T. Yoshinaga, M. Sowa, Modular design structure and high-level prototyping for novel embedded processor core, in Proceedings of the 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC’2005), Nagasaki, 340–349 Dec 6–9 2005

    Google Scholar 

  14. V. Tiwari, S. Malik, Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 17(10), 1051–1060 (1998)

    Article  Google Scholar 

  15. A. Abnous, J. Rabaey, Ultra-low-power domain-specific multimedia processors, in (Proceedings of the IEEE VLSI Signal Processing Workshop, IEEE press, 459–464 1996

    Google Scholar 

  16. J. Liang et al., An architecture and compiler for scalable on-chip communication. IEEE Trans. VLSI Syst. 12(7), 711–726 (2004)

    Article  Google Scholar 

  17. J. Rabaey, L. Guerra, R.Mehra, Design guidance in the power Dimension, in Proceedings of the ICASSP, 1995

    Google Scholar 

  18. C.L. Su, M. Alvin Despain, cache designs for energy efficiency, in Proceedings of the 28th Hawaii International Conference on System Science, 1995

    Google Scholar 

  19. H. Mehta, R. M. Owens, M.J. Irwin, R. Chen, D. Ghosh, Techniques for low energy software, in Internatzonal Symposzum of Low Power Electronics and Deszgn, IEEE/ACM, 72–75 1997

    Google Scholar 

  20. F. Doughs, P. Krishnan, B. Marsh, Thwarting the power hungry disk, in Proceedings of the 1991 Winter USENIX Conference, 1994

    Google Scholar 

  21. F. Douglis, F. Kaashoek, B. March, R. Caceres, K. Li, J. Tauber, Storage alternative for mobile computers, in Proceedings of the first USENIX Symposimum on Operating Systems Design and Implemnetation, 1994

    Google Scholar 

  22. K. Li, R. Kumpf, P. Horton, T. Anderson, A quantitative analysis of disk drive power management in portable computers, in Proceedings of the 1994 Winter USENIX, 1994

    Google Scholar 

  23. P. Erik, P. Harris, W. Steven, E.W. Pence, S. Kirkpatrick, Technology directions for portable computers. in Proceedings of the IEEE, 83b(4) 63–57 1995

    Google Scholar 

  24. K. Govil, E. Chan, H. Wasserman. Comparing algorithms for dynamic speed-setting of a low-power cpu, In First ACM International Conference on Mobile Computing and Networking (MOBICOM), 1995

    Google Scholar 

  25. J.R. Lorch, A.J. Smith. Reducing processor power consumption by improving processor time management in a single user operating system, in Second ACM International Conference on Mobile Computing and Networking (MOBICOM), 1996

    Google Scholar 

  26. M. Weiser, B. Welch, A. Demers, S. Shenker. Schedlibng for reduced cpu energy. inProceedings of the First Symposium on Operating System Design and Implementation (OSDI), 1994

    Google Scholar 

  27. J. Lorch, A complete picture of the energy consumption of a portable computer. Master’s thesis, Department of Computer Science, University of California at Berkeley, 1995

    Google Scholar 

  28. J.R. Lorch, A.J. Smith, Software strategies for portable computer energy management. IEEE Pers. Commun. 5(3), 60–73 (1998)

    Article  Google Scholar 

  29. V. Tiwari, S. Malik, A. Wolfe, Power analysis of embedded software: a first step towards software power minimization. IEEE Trans. Very Large Scale Integr. 2(4), 437–445 (1994)

    Article  Google Scholar 

  30. F. Wolf, Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Process (Kluwer Academic Publishers, The Netherlands, 2002). ISBN 1-4020-7135-3

    Book  Google Scholar 

  31. Intel Corporation. Mobile power guidelines (2000), ftp://download.intel.com/design/mobile/ intelpower/mpg99r1.pdf, Accessed Dec 1998

  32. Intel Corporation: Mobile intel pentium III processor in BGA2 and micro-PGA2 packages, revision 7.0, (2001)

    Google Scholar 

  33. P.J.M. Havinga, G.J.M. Smit, Energy-efficient wireless networking for multimedia applications, in wireless communications and mobile computing. Wirel. Commun. Mob. Comput. 1, 165–184 (2001)

    Article  Google Scholar 

  34. K.M. Sivalingam, J.C. Chen, P. Agrawal, M. Srivastava, Design and analysis of low-power access protocols for wireless and mobile ATM networks. Wirel. Netw. 6(1), 73–87 (2000)

    Article  MATH  Google Scholar 

  35. F. Akyildiz, S. Weilian, S. Yogesh, E. Cayirci, A Survey on sensor networks. IEEE Commun. Mag. 40(8), 102–114 (2002)

    Article  Google Scholar 

  36. P.J. Havinga, G. Smit, M. Bos, Energy-efficient wireless ATM design, in (Proceedings wmATM), 2–4 June 1999

    Google Scholar 

  37. H. Balakrishnan, V. Enkata, N. Padmanabhan, A comparison of mechanisms for improving tcp performance over wireless links. IEEE/ACM Trans. Netw. 5(6), 756–769 (1997)

    Article  Google Scholar 

  38. J. Kistler, Disconnected operation in a distributed file system, Ph.D. thesis, Carnegie Mellon University, School of Computer Science, 1993

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Computer Science and Engineering, The University of Aizu, Aizu-Wakamatsu, Fukushima, Japan

    Abderazek Ben Abdallah

Authors
  1. Abderazek Ben Abdallah
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Abderazek Ben Abdallah .

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer Nature Singapore Pte Ltd.

About this chapter

Cite this chapter

Ben Abdallah, A. (2017). Power Optimization Techniques for Multicore SoCs. In: Advanced Multicore Systems-On-Chip. Springer, Singapore. https://doi.org/10.1007/978-981-10-6092-2_8

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-6092-2_8

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-6091-5

  • Online ISBN: 978-981-10-6092-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation