Abstract
An algorithm is developed for arithmetic operation with reduced circuit complexity and memory by using binary logarithm operations, and along with this comparative error analysis of logarithmic multiplier is discussed. Since logarithm of a binary number is approximated by shifting and counting the bits itself, thus no look-up table (LUT) or logic cell is required but errors are introduced which can be reduced based on parallel computation.
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Ali, S.W., Sharma, M., Tripathy, M.R. (2018). Efficient Method to Implement Arithmetic Operations Using Binary Logarithmic Algorithms for Reduced Circuit Complexity with Error Analysis. In: Singh, R., Choudhury, S., Gehlot, A. (eds) Intelligent Communication, Control and Devices. Advances in Intelligent Systems and Computing, vol 624. Springer, Singapore. https://doi.org/10.1007/978-981-10-5903-2_93
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DOI: https://doi.org/10.1007/978-981-10-5903-2_93
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