Efficient Method to Implement Arithmetic Operations Using Binary Logarithmic Algorithms for Reduced Circuit Complexity with Error Analysis

  • Sayyed Waize Ali
  • Manish Sharma
  • M. R. Tripathy
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)

Abstract

An algorithm is developed for arithmetic operation with reduced circuit complexity and memory by using binary logarithm operations, and along with this comparative error analysis of logarithmic multiplier is discussed. Since logarithm of a binary number is approximated by shifting and counting the bits itself, thus no look-up table (LUT) or logic cell is required but errors are introduced which can be reduced based on parallel computation.

Keywords

Logarithmic number system (LNS) Logarithmic multiplier Mitchell’s algorithm Parallel processing 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Sayyed Waize Ali
    • 1
  • Manish Sharma
    • 1
  • M. R. Tripathy
    • 1
  1. 1.Amity School of Engineering and Technology, Amity UniversityNoidaIndia

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