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Efficient Method to Implement Arithmetic Operations Using Binary Logarithmic Algorithms for Reduced Circuit Complexity with Error Analysis

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Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 624))

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Abstract

An algorithm is developed for arithmetic operation with reduced circuit complexity and memory by using binary logarithm operations, and along with this comparative error analysis of logarithmic multiplier is discussed. Since logarithm of a binary number is approximated by shifting and counting the bits itself, thus no look-up table (LUT) or logic cell is required but errors are introduced which can be reduced based on parallel computation.

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References

  1. Demetrious K. Kostopoulos “An Algorithm for Computation of Binary Logarithm”, IEEE transaction on electronic computer, vol 40, No. 11, November 1991.

    Google Scholar 

  2. John N. Mitchell, “Computer Multiplication and Division using Binary Logarithm”, IEEE transaction on electronic computer August 1962.

    Google Scholar 

  3. Mahalingum and N. Rangantathan “Improving accuracy in Binary logarithm using operand Decomposition.” IEEE Transaction on Computers, Vol. 55 No. 2, pp 1523–1535, December 2016.

    Google Scholar 

  4. Tso-Bing Juang, Han-Lung-Kuo and Kai-Shaing, Jan “ Lower error and area efficient antilogarithmic converters with bit correction Schemes.” Journal of the Chinese Institute of Engineers, 2015.

    Google Scholar 

  5. P. Saha, A. Banerjee, A. Dandapat and P. Bhattacharya “High speed multipler using high accuracy floating point logarithmic number system”. Scientia Iranica Transaction D: Computer Science and Engineering and Electrical Engineering, Vol 21 No.3, pp. 826–841, 2014

    Google Scholar 

  6. R. K. Agrawal, and H. M. Kittur,” ASIC Based Logarithmic Multiplier using iterative pipelined architecture,” IEEE Conference on information & Communication Technologies (ICT) pp. 362–366 2013.

    Google Scholar 

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Correspondence to Sayyed Waize Ali .

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Ali, S.W., Sharma, M., Tripathy, M.R. (2018). Efficient Method to Implement Arithmetic Operations Using Binary Logarithmic Algorithms for Reduced Circuit Complexity with Error Analysis. In: Singh, R., Choudhury, S., Gehlot, A. (eds) Intelligent Communication, Control and Devices. Advances in Intelligent Systems and Computing, vol 624. Springer, Singapore. https://doi.org/10.1007/978-981-10-5903-2_93

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  • DOI: https://doi.org/10.1007/978-981-10-5903-2_93

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-5902-5

  • Online ISBN: 978-981-10-5903-2

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