Line-Based Successive Cancellation Decoder with Reduced Complexity
The error-correcting codes which achieve Shannon’s channel capacity are polar codes for infinite length. In this, we propose an efficient implementation for SC polar decoders with O(log2N) processing elements, where N is code block length. Here, SC decoding processing unit is implemented in logarithmic domain, thereby reducing the multiplication and division operations and low-complex partial sum logic. This decoder architecture has a low dispensation density that allows large polar codes to put into practice. Simulation is done using Xilinx, and simulation results are presented.
KeywordsSuccessive cancellation decoder VLSI Polar codes Partial sum logic
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