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Impact of Buried Oxide Layer Thickness on the Performance Parameters of SOI FinFET at 22 nm Node Technology

  • Ravneet Kaur
  • Charu Madhu
  • Deepti Singh
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)

Abstract

In CMOS technology, as we decrease the gate length of MOSFET from µm to nm, its performance is effected due to increased short-channel effect (SCE) and leakage current (Xie et al. in IEEE Trans Electron Devices 59, 2012 [1]; Loan, Quresh, and Sundar Kumar Iyer in IEEE Trans Electron Devices 5, 2010 [2]). Multigate transistors like double gate, tri-gate transistors, FinFETs are proposed to reduce SCEs which finally result in improvement of current flowing through device (Agostinelli et al. in IEEE Trans Very Large Scale Integr (VLSI) Syst 5, 2010 [3]; Singha et al. in Optimization of Underlap Length for DGMOSFET and FinFET, 2015 [4]; Sahu et al. in J Microelectron, Electr Compon Mater 44(2), 2015 [5]). Buried oxide layer is introduced in the substrate of FinFET to decrease parasitic capacitance which is formed between source/drain region and substrate of FinFET (Sun et al. in IEEE Trans Electron Devices 58, 2011 [6]; Ponton in IEEE Trans Circuits Syst 56(5), 2009 [7]). Thus, the paper highlights the effect of variation in buried oxide layer thickness of SOI FinFET on electrical parameters like threshold voltage, drain-induced barrier lowering (DIBL), on current, off current, on/off current ratio. Various simulation results are shown in the research paper using TCAD software.

Keywords

Silicon-on-insulator (SOI) Short-channel effects (SCE) Drain-induced barrier lowering (DIBL) Fin-shaped field-effect transistor (FinFET) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.University Institute of Engineering and Technology, Panjab UniversityChandigarhIndia

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