Impact of Buried Oxide Layer Thickness on the Performance Parameters of SOI FinFET at 22 nm Node Technology

  • Ravneet Kaur
  • Charu Madhu
  • Deepti Singh
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)


In CMOS technology, as we decrease the gate length of MOSFET from µm to nm, its performance is effected due to increased short-channel effect (SCE) and leakage current (Xie et al. in IEEE Trans Electron Devices 59, 2012 [1]; Loan, Quresh, and Sundar Kumar Iyer in IEEE Trans Electron Devices 5, 2010 [2]). Multigate transistors like double gate, tri-gate transistors, FinFETs are proposed to reduce SCEs which finally result in improvement of current flowing through device (Agostinelli et al. in IEEE Trans Very Large Scale Integr (VLSI) Syst 5, 2010 [3]; Singha et al. in Optimization of Underlap Length for DGMOSFET and FinFET, 2015 [4]; Sahu et al. in J Microelectron, Electr Compon Mater 44(2), 2015 [5]). Buried oxide layer is introduced in the substrate of FinFET to decrease parasitic capacitance which is formed between source/drain region and substrate of FinFET (Sun et al. in IEEE Trans Electron Devices 58, 2011 [6]; Ponton in IEEE Trans Circuits Syst 56(5), 2009 [7]). Thus, the paper highlights the effect of variation in buried oxide layer thickness of SOI FinFET on electrical parameters like threshold voltage, drain-induced barrier lowering (DIBL), on current, off current, on/off current ratio. Various simulation results are shown in the research paper using TCAD software.


Silicon-on-insulator (SOI) Short-channel effects (SCE) Drain-induced barrier lowering (DIBL) Fin-shaped field-effect transistor (FinFET) 


  1. 1.
    Qian Xie, Jun Xu, and Yuan Taur “Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, JUNE 2012.Google Scholar
  2. 2.
    Sajad A. Loan, S. Quresh, and S. Sundar Kumar Iyer, “A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 5, MARCH 2010.Google Scholar
  3. 3.
    Matteo Agostinelli, Massimo Alioto, David Esseni and Luca Selmi, “Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, FEBRUARY 2010.Google Scholar
  4. 4.
    D. Singha, K. P Pradhana, S. K. Mohapatraa, P. K. Sahua “Optimization of Underlap Length for DGMOSFET and FinFET” 3rd International Conference on Recent Trends in Computing 2015 (ICRTC-2015).Google Scholar
  5. 5.
    P. K. Sahu, S. K. Mohapatra, K. P. Pradhan “Impact of Downscaling on Analog/RF Performance of sub-100 nm GS-DG MOSFET” Journal of Microelectronics, Electronic Components and Materials, Vol. 44, No. 2, 2014.Google Scholar
  6. 6.
    Xin Sun, Victor Moroz, Nattapol Damrongplasit, Changhwan Shin and Tsu-Jae King Liu “Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 10, OCTOBER 2011.Google Scholar
  7. 7.
    Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Domagoj ˇ Siprak, and Gerhard Knoblinger, “Design of Ultra-Wideband Low-Noise Amplifiers in 45 nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices” IEEE Transaction on Circuits and System, Vol. no. 56, No. 5, May 2009.Google Scholar
  8. 8.
    Jong-Ho Lee “Bulk FinFETs: Design at 14 nm Node and Key Characteristics” Springer Science, Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, Springer science + business media 2016.Google Scholar
  9. 9.
    T. Chiarella, L. Witters, A. Mercha, C. Kerner, R. Dittrich], M. Rakowski, C. Ortolland, L.-A. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, P. AbsiI, S. Biesemans and T. Hoffmann “Migrating from Planar to FinFET for Further CMOS Scaling: SOI or Bulk?”, Proceedings of the European Solid State Device Research Conference, 2009.Google Scholar
  10. 10.
    Mirko Poljak, Vladimir Jovanović, Tomislav Suligoj “SOI vs. Bulk FinFET: Body Doping and Corner Effects Influence on Device Characteristics” Electrotechnical conference, IEEE Transaction of Electronic Devices, 2008.Google Scholar
  11. 11.
    S. Krivec, H. Prgić, M. Poljak and T. Suligoj “Comparison of RF performance between 20 nm-gate bulk and SOI FinFET” 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2014.Google Scholar
  12. 12.
    Anterpreet Gill, Charu Madhu, Pardeep Kaur “Investigation of short channel effects in Bulk MOSFET and SOI FinFET at 20 nm node technology” IEEE INDICON 2015.Google Scholar
  13. 13.
    Takashi Matsukawa, Yongxun Liu, Shin-Ichi O’uchi, Kazuhiko Endo, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Hiroyuki Ota, Shinji Migita, Yukinori Morita, Wataru Mizubayashi, Kunihiro Sakamoto, and Meishoku Masahara, “Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 8, AUGUST 2012.Google Scholar
  14. 14.
    Ulayil Sajesh Kumar and Valipe Ramgopal Rao, “A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 1, JANUARY 2016.Google Scholar
  15. 15.
    Raghvendra Sahai Saxena and M. Jagadesh Kumar “Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012.Google Scholar
  16. 16.
    Farshad Moradi, Sumeet Kumar Gupta, Georgios Panagopoulos, Dag T. Wisland, Hamid Mahmoodi, and Kaushik Roy, “Asymmetrically Doped FinFETs for Low-Power Robust SRAMs” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 12, DECEMBER 2011.Google Scholar
  17. 17.
    Zhe Xu, Jinyan Wang, Yong Cai, Jingqian Liu, Zhen Yang, Xiaoping Li, Maojun Wang, Zhenchuang Yang, Bin Xie, Min Yu, Wengang Wu, Xiaohua Ma, Jincheng Zhang and “300 °C operation of normally-off AlGaN/GaN MOSFET with low leakage current and high on/off current ratio” Electronics Letters,Volume: 50, IEEE, February 2014.Google Scholar
  18. 18.
    Vishal Narula, Charu Narula, Jatinder singh “Investigating Short Channel Effects and Performance Parameters of Double Gate Junctionless Transistor at Various Technology Nodes” International Conferences on Recent Advances in Engineering & Computational sciences (RAECS), December 2015.Google Scholar
  19. 19.
    Mahender Veshala, Ramchander Jatooth, Kota Rajesh Reddy, “Reduction of Short-Channel Effects in FinFET” International Journal of Engineering and Innovative Technology (IJEIT), Volume 2, Issue 9, March 2013.Google Scholar
  20. 20.
    Anurag Chaudhry and M. Jagadesh Kumar, “Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review”, IEEE Trans. on Device and Materials Reliability, Vol.4, pp. 99–109, March 2004.Google Scholar

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© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.University Institute of Engineering and Technology, Panjab UniversityChandigarhIndia

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