Abstract
This paper proposes an FPGA architecture for a 512-bit AES implementation using a pre-ciphered lookup table approach. The hardware realization uses a 512-bit block message and a 512-bit key. The architecture is designed to give an increased throughput for applications were session keys are used for communication. The architecture exploits the fact that session key does not change for substantial duration for an entire session; therefore, a pre-ciphered lookup table can be used to enhance the encryption throughput. The design is suitable for applications where communication is performed in sessions and the key does not alter frequently, such as HTTP, Telnet remote login session in the application layer. An FPGA architecture is developed using Verilog HDL and synthesized using Virtex-7 device which shows a 290.71% increase in the throughput achieved in comparison with the previous implementation.
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Kumar, V., Pandey, P.S., Ranjan, P. (2018). A High-Throughput FPGA-Based Architecture for Advanced Encryption Standard: AES-512 Using Pre-ciphered Lookup Table. In: Singh, R., Choudhury, S., Gehlot, A. (eds) Intelligent Communication, Control and Devices. Advances in Intelligent Systems and Computing, vol 624. Springer, Singapore. https://doi.org/10.1007/978-981-10-5903-2_5
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DOI: https://doi.org/10.1007/978-981-10-5903-2_5
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