Abstract
The proposed idea is implementation of a multiplier by using operand decomposition through pipelining so as to do fast computation maximum error reduction (Patricio Bulić et al., A Simple Pipelined Logarithmic Multiplier, IEEE International conference on computer Design, 2010 [1], Mahalingam and Rangantathan, IEEE T Comput, 55(2): 1523–1535, 2006. [2], Mclaren, Preceedings of IEEE International SOC Conference 2003, 53–56, 2003 [3]). Implementing the proposed idea with iterative pipelined architecture with less switching activity and this architecture can be opted where speed and accuracy are preferred over complexity.
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References
Patricio Bulić; Zdenka Babić; Aleksej Avramović, A Simple Pipelined Logarithmic Multiplier, IEEE International conference on computer Design 2010.
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Shikha, P., Sharma, M., Rajput, S. (2018). Iterative Basic Block Pipelining Implementation as Fast Computation Technique. In: Singh, R., Choudhury, S., Gehlot, A. (eds) Intelligent Communication, Control and Devices. Advances in Intelligent Systems and Computing, vol 624. Springer, Singapore. https://doi.org/10.1007/978-981-10-5903-2_165
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DOI: https://doi.org/10.1007/978-981-10-5903-2_165
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