Iterative Basic Block Pipelining Implementation as Fast Computation Technique

  • Parul Shikha
  • Manish Sharma
  • Sachin Rajput
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)


The proposed idea is implementation of a multiplier by using operand decomposition through pipelining so as to do fast computation maximum error reduction (Patricio Bulić et al., A Simple Pipelined Logarithmic Multiplier, IEEE International conference on computer Design, 2010 [1], Mahalingam and Rangantathan, IEEE T Comput, 55(2): 1523–1535, 2006. [2], Mclaren, Preceedings of IEEE International SOC Conference 2003, 53–56, 2003 [3]). Implementing the proposed idea with iterative pipelined architecture with less switching activity and this architecture can be opted where speed and accuracy are preferred over complexity.


Operand decomposition Mitchel’s algorithm Pipelining 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Amity UniversityNoidaIndia

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