Abstract
The growth of electronic chip technique has led to frequent occurrence of intellectual property (IP) disputes. It seriously affects rapid and healthy development of semiconductor industry. To address the disputes, many IP protection methods are proposed in these years, such as IP watermarking. It is a novel technique to hide secrets in IP core to prove original ownership. This chapter focuses on two issues: how to hide secrets in IP circuit and how to authenticate IP ownership. Four types of IP watermarking methods will be concretely introduced in this chapter. (1) FPGA based IP watermarking technique. (2) FSM based IP watermarking technique. (3) DFT based IP watermarking technique. (4) Self-recoverable dual IP watermarking technique. The experiments show that the proposed schemes have low resource overhead by comparing with other schemes. Meanwhile the resistance to attacks of the watermark is encouraging as well.
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References
Koushanfar F, Fazzari S, McCants C, et al. 2012. Can EDA combat the rise of electronic counterfeiting? In Proceedings of 2012 49th ACM/EDAC/IEEE design automation conference (DAC), 133–138.
Majzoobi M, Koushanfar F, Devadas S. 2010. FPGA PUF using Programmable Delay Lines. In Proceedings of information forensics and security (WIFS), 51–65.
Guajardo J, Guneysu T, Kumar S S, et al. 2009. Secure IP-block distribution for hardware devices. In IEEE international workshop on hardware-oriented security and trust, 82–89.
Kirovski D, Potkonjak M. Local watermarks: Methodology and application to behavioral synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1277–1283.
Marsh C, Kean T. 2007. A security tagging scheme for ASIC designs and intellectual property cores. Design & Reuse, 57–64.
Goren S, Ugurdag H F, Yildiz A ,Ozkurt O. 2010. FPGA design security with time division multiplexed PUFs. In Proceedings of international conference on high performance computing and simulation (HPCS), 608–614.
Lach J, Mangione W H, Potkonjak M. 2001. Fingerprinting techniques for field-programmable gate array intellectual property protection. IEEE transactions on computer-aided design of integrated circuits and systems, 1253–1261
Guneysu T, Moller B, Paar C. 2007. Dynamic intellectual property protection for reconfigurable devices. In Proceedings of the 15th annual IEEE symposium on FPT, 287–288
Li, D., W. Zheng, and M. Zhang. 2007. Development of IP watermarking techniques. Journal of Circuit and Systems 12(4): 84–92.
Roy J A, Koushanfar F, Markov I L. 2008. EPIC: Ending piracy of integrated circuits. In Proceedings of the conference on design, Europe, 1069–1074.
Yip K, Ng T. 2000. Partial-encryption technique for intellectual property protection of FPGA-based products. IEEE Transactions on Consumer Electronics, 183–190.
Nie T, Liu H, Zhou L. 2012. A time-constrained watermarking technique on FPGA. In Proceedings of 2012 international conference on industrial control and electronics engineering (ICICEE), 795–798.
Khan M and Tragoudas S. 2005. Rewiring for watermarking digital circuit netlists. IEEE transactions on computer-aided design of integrated circuits and systems, 1132–1137.
Liang, W., X. Sun, Z. Xia, and J. Long. 2011. A chaotic IP watermarking in physical layout level based on FPGA. Radioengineering 20(1): 118–125.
Liang, W., K. Wu, H. Zhou, and Y. Xie. 2015. TDCM: An IP watermarking algorithm based on two-dimensional chaotic mapping. Computer Science and Information Systems 12(2): 823–841.
Liang W, Long J, Chen X, Xiao W. 2016. Publicly verifiable blind detection for intellectual property watermarks through zero-knowledge protocol. International Journal of System Assurance Engineering and Management, 738–981.
Xu J B, Long J, Liang W. 2011. A DFA-based distributed IP watermarking method using data compression technique. Journal of Convergence Information Technology, 152–160.
Raj N, Josprakash, et al. 2011. Behavioral level watermarking techniques for IP identification based on testing in SOC design. In Proceedings of international conference on information technology and mobile communication, 485–488.
Castillo E, Meyer-Baese U, GarcÃa A. 2007. IPP@HDL: Efficient intellectual property protection scheme for IP cores. IEEE Transactions on VLSI Systems, 578–591.
Sun, X., M. Zhang, and H. Zhang. 2013. Two-Dimension Chaotic-Multivariate Signature System 10(1). 1694–0814.
Basu, A., D.B. Roy, and D. Banerjee. 2011. FPGA implementation of IP protection through visual information hiding. International Journal of Engineering Science and Technology 3(5): 4191–4199.
Torunoglu I, Charbon E. 2000. Watermarking-based copyright protection of sequential functions. IEEE Journal of Solid-State Circuits, 434–440.
Oliveira A L. 2001. Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1101–1117.
Abdel-Hamid A T, Tahar S. 2008. Fragile IP watermarking techniques. In Proceedings of NASA/ESA conference on adaptive hardware and systems. Noordwijk, 513–519.
Cui A, Chang C H, Tahar S. 2008. IP watermarking using incremental technology mapping at logic synthesis level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1565–1570.
Yuan L and Qu G. 2004. Information hiding in finite state machine. In Information hiding workshop, 340–354.
Abdel-Hamid A T, Tahar S, and Aboulhamid E M. 2006. Finite state machine IP watermarking: A tutorial. In Proceedings of the first NASA/ESA conference on adaptive hardware and systems (AHS’06), 457–464.
Fan Y. 2008. Testing-based watermarking techniques for intellectual-property identification in SOC design. IEEE Transactions on Instrumentation and Measurement, 467–479.
Saha D, Sur-Kolay S. 2010. A unified approach for IP protection across design phases in a packaged chip. In Proceedings of 23rd international conference on VLSI design, 105–110.
Cui A, Chang C H. 2012. A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. In Proceedings of 2012 IEEE Asia pacific conference on circuits and systems (APCCAS), 412–415.
Khan, M., and S. Tragoudas. 2005. Rewiring for watermarking digital circuit netlists. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(7): 1132–1137.
Cui, A., Chang, C. H. 2008. Intellectual property authentication by watermarking scan chain in design-for-testability flow. In Proceedings of International Symposium on CAS, 2645–2648.
Kirovski, D., Y.Y. Hwang, et al. 2006. Protecting combinational logic synthesis solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(12): 2687–2696.
Xu, J., Y. Sheng, W. Liang, L. Peng, and J. Long. 2016. A high polymeric mutual mapping IP watermarking algorithm for FPGA design. Journal of Computational and Theoretical Nanoscience 13(1): 186–193.
Acknowledgements
This work is supported by the National Science Foundation of China (61572188), the Research Project supported by Xiamen University of Technology (YKJ15019R, YSK15003R), Xiamen Science and Technology Foundation (3502Z20173035).
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Liang, W., Long, J., Zhang, D., Li, X., Huang, Y. (2018). Study on IP Protection Techniques for Integrated Circuit in IOT Environment. In: Di Martino, B., Li, KC., Yang, L., Esposito, A. (eds) Internet of Everything. Internet of Things. Springer, Singapore. https://doi.org/10.1007/978-981-10-5861-5_9
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DOI: https://doi.org/10.1007/978-981-10-5861-5_9
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