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Design of Power Efficient SRAM on FPGA

Conference paper
Part of the Lecture Notes in Mechanical Engineering book series (LNME)

Abstract

Low power based-Static RAM is designed using LVTTL and Mobile-DDR IO Standards on 28 nm Artix-7 FPGA. And at different range of operating frequency power dissipation has been calculated and amount of power dissipation by using LVTTL and Mobile-DDR IO buffer has been compared with each other, Mobile-DDR is more power efficient. At operating frequency of 1 GHz, 2 GHz, and 3 GHz, Mobile-DDR is used in place of LVTTL then 31.26%, 43.14%, and 47.45% total power can be saved, respectively.

Keywords

LVTTL Mobile-DDR FPGA SRAM IO buffer Low power High speed Artix-7 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication, G.L.A. UniversityMathuraIndia

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