Abstract
The Internet of Things (IoTs) applications have garnered its interest to realize low-power memory circuit based on emerging nanoscale transistors for its data processing unit. Therefore, in this work, we focussed on tunneling mechanism-based tunnel field-effect transistor (TFET) which can be a suitable option beyond-CMOS devices for designing reliable and efficient memory circuits for its key sensing and data processing unit. However, this work is further extended toward low-power design strategy to meet the essential requirements of IoT applications. For this purpose, a junctionless (JL) TFET based on work-function engineering is reported in this work, where a high-k material (HfO\(_{2}\)) adjacent to the SiO\(_{2}\) toward source side is considered underneath the gate region to improve the ON-current of the proposed device. The main benefits of junctionless architecture is that it reduces the fabrication complexity, high thermal budget, and is free from random dopant fluctuations (RDFs). The significant benefits in terms of hold, read, and write static noise margin (SNM) of JLTFET-based six-transistor (6T) memory cell enables its potential application for IoT memory unit.
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References
L. Atzori, A. Iera and G. Morabito, The internet of things: A survey, Comput. Netw., vol. 54, no. 15, pp. 2787–2805, 2010.
H. Scott et al., A low-voltage processor for sensing applications with picowatt standby mode, JSSCC 2009.
K. Roy and S. Prasad, Low-Power CMOS VLSI Circuit Design. 1\(^{st}\) ed. New York, NY, USA: Wiley, 2000.
B. Zimmer et al., SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 12, pp. 853–857, 2012.
A. C. Seabaugh and Q. Zhang, Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec. 2010.
M. A. Ionescu and H. Riel, Tunnel field-effect transistors as energy efficient electronic switches, Nature, vol. 479, pp. 329–337, 2011.
K. Boucart and A. M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725–1733, Jul. 2007.
M. J. Kumar and S. Janardhanan, Doping-Less Tunnel Field Effect Transistor: Design and Investigation, IEEE Trans. Electron Devices, vol. 16, no. 10, pp. 3285-3290, Oct. 2013.
B. Ghosh, M. W. Akram, Junctionless Tunnel Field Effect Transistor, IEEE Electron Device Letter, vol. 34, no. 5, pp. 584–586, May. 2013.
K. Swaminathan, H. Liu, X. Li et al., Steep slope devices: Enabling new architectural paradigms, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, pp. 1–6, 2014.
X. Li et al., RF-powered systems using steep-slope devices, New Circuits and Systems Conference (NEWCAS), 2014.
S. Kim, et al., Ambient RF Energy-Harvesting Technologies for Self-Sustainable Standalone Wireless Sensor Platforms, Proc. IEEE, vol. 102, no. 11, pp. 1649–1666, 2014.
M. A. G. de Brito et al., Evaluation of the Main MPPT Techniques for Photovoltaic Applications, IEEE Transactions on Industrial Electronics, vol. 60, no. 3, pp. 1156–1167, March 2013.
Silvaco Interantional, ATLAS Users Manual, A 2D-3D Numerical Device Simulator, (http://www.silvaco.com).
S. Ahish, D. Sharma, M. H. Vasantha, Y. B. N. Kumar, Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field-effect transistor, Superlattices and Microstructures, vol. 94, pp. 119–130, Jun. 2016.
S. Strangio, P. Palestri, M. Lanuzza, F. Crupi, D. Esseni and L. Selmi, Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits, IEEE Trans. Electron Devices, vol. 63, no. 7, pp. 2749–2756, July 2016.
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Anju, Pandey, S., Yadav, S., Nigam, K., Sharma, D., Kondekar, P.N. (2018). Realization of Junctionless TFET-Based Power Efficient 6T SRAM Memory Cell for Internet of Things Applications. In: Somani, A., Srivastava, S., Mundra, A., Rawat, S. (eds) Proceedings of First International Conference on Smart System, Innovations and Computing. Smart Innovation, Systems and Technologies, vol 79. Springer, Singapore. https://doi.org/10.1007/978-981-10-5828-8_49
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DOI: https://doi.org/10.1007/978-981-10-5828-8_49
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