Abstract
Using extensive numerical device simulation, we investigate the influence of sidewall spacers on the analog/RF performance of double-gate junctionless transistors at channel length of 30 nm. Our findings reveal that peak transconductance and peak intrinsic gain increase by 5.2 and 71.3% for spacer dielectric constant k = 30 as compared to the respective values for k = 3.9, while peak unity gain cut-off frequency increases by 37% for k = 3.9 compared with the value for k = 30. The transconductance generation factor is found to be less sensitive to the variation in k. With increasing k the output conductance becomes less for low gate overdrive voltage V GT while it shows a reverse trend for higher V GT. It is evident from our studies that peak transconductance, peak transconductance generation factor, peak gain, and peak cut-off frequency increase by 13, 10, 27, and 20%, respectively, for spacer length of 5 nm compared with the corresponding values for spacer length of 15 nm. However, with a larger spacer length, the output conductance exhibits reduced value for lower V GT, while it becomes comparable with the values for smaller spacer lengths as V GT increases.
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The first author acknowledges TEQIP Phase II, University of Calcutta for providing financial support.
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Roy, D., Biswas, A. (2018). Impact of Sidewall Spacer Layers on the Analog/RF Performance of Nanoscale Double-Gate Junctionless Transistors. In: Nath, V. (eds) Proceedings of the International Conference on Microelectronics, Computing & Communication Systems. Lecture Notes in Electrical Engineering, vol 453. Springer, Singapore. https://doi.org/10.1007/978-981-10-5565-2_8
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DOI: https://doi.org/10.1007/978-981-10-5565-2_8
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