Skip to main content

Fabrication and Investigation of Low-Voltage Programmable Flash Memory Gate Stack

  • Conference paper
  • First Online:
Proceedings of the International Conference on Microelectronics, Computing & Communication Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 453))

Abstract

In this paper, fabrication, characterization, and analysis of a FGMOS gate stack employing ultra-thin tunnel oxide of 3 nm thickness are discussed. Apart from basic C-V and G-V profiles, high-frequency hysteresis curve has been investigated and device-level parameters are extracted. Use of ultra-thin tunnel oxide has facilitated direct tunneling mechanism at program/erase voltages of 10 V for 200 ms and −8 V for 40 ms, respectively. Excellent memory window of 1.2 V has been obtained. Frequency-dependent capacitance and reliability-related profiles are also studied. The device is useful for power-efficient non-real-time applications like data logging, biometric security, backup servers.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

References

  1. K. Sung-Mo, L. Yusuf, S.-M. Yoo, CMOS Digital Integrated Circuits: Analysis and Design, 3rd edn. (TMH, New Delhi, India, 2003)

    Google Scholar 

  2. M. Jan, Rabaey, Anantha Chandrakasan, Borivoje Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Pearson Prentice-Hall, Delhi, India, 2008)

    Google Scholar 

  3. Datalight Inc (2008) Choosing NAND or NOR Flash Memory: Tradeoffs and Strategies. Available: http://www.datalight.com. 8 July 2008

  4. Toshiba America Electronic Components, Inc. (2011). NAND vs. NOR Flash Memory Technology Overview. Available: www.mitchellcreativegroup.com. 21 May 2011

  5. Jan De Blauwe, Nanocrystal nonvolatile memory devices. IEEE Trans. Nanotechnol. 1(1), 72–77 (2002)

    Article  Google Scholar 

  6. T-H. Hou, J. Lee, J.T. Shaw, E.C. Kan, Flash Memory Scaling: From Material Selection to Performance Improvement (2007). Available: www.researchgate.net. Dec 2007

  7. Y. He, Z. Zhang, L. Wang, W. Li, J. He, An interesting phenomenon in the C-V Measurements of Nanocrystal Based MOS capacitor. Proc. IEEE Workshop Electron. Devices Semicond. Technol. 129–132 (2007)

    Google Scholar 

  8. International Technology Roadmap for Semiconductors (ITRS) (2001), Available: http://www.itrs.net [Online]

  9. International Technology Roadmap for Semiconductors (ITRS) (2003), Available: http://www.itrs.net [Online]

  10. International Technology Roadmap for Semiconductors (ITRS) (2005), Available: http://www.itrs.net [Online]

  11. International Technology Roadmap for Semiconductors (ITRS) (2013), Available: http://www.itrs.net [Online]

  12. Y. Fujisajki, Overview of emerging semiconductor non-volatile memories, IEICE Electron. Express. 9(10), 908–925 (2012)

    Google Scholar 

  13. O-Y. Wong, R. Wong, W-S. Tarn, C-W. Kok, An overview of charge pumping circuits for flash memory applications, Proc. IEEE Int. Conf. ASIC (ASICON), 116–119 (2011)

    Google Scholar 

  14. International Technology Roadmap for Semiconductors (ITRS) (2010). Available: http://www.itrs.net [Online]

  15. International Technology Roadmap for Semiconductors (ITRS) (2011). Available: http://www.itrs.net [Online]

  16. International Technology Roadmap for Semiconductors (ITRS) (2012). Available: http://www.itrs.net [Online]

  17. O. Khouri, S. Gregori, R. Micheloni, D. Soltesz, G. Torelli, Low Output Resistance Charge Pump for Flash Memory Programming (Design and Testing, Proc. IEEE Int. Workshop on Memory Technology, 2001), pp. 99–104

    Google Scholar 

  18. G. Palumbo, D. Pappalardo, Charge pump circuits: an overview on design strategies and topologies. IEEE Circ. Syst. Mag. 10(1), 31–45 (2010)

    Google Scholar 

  19. S.A. Bhalerao, A.V. Chaudhary, R.M. Patrikar, A CMOS low voltage charge pump. Proc. IEEE 6th Int. Conf. Embed. Syst. 20th Int. Conf. VLSI Des. 941–946 (2007)

    Google Scholar 

  20. B.R. Gregoire, A compact switched-capacitor regulated charge pump power supply. IEEE J. Solid-State Circ. 41(8), 1944–1953 (2006)

    Google Scholar 

  21. S.W. Choi, D.J. kim, J. Chung, B.S. Han, J. Park, Efficiency optimization of charge pump circuit in NAND FLASH memory. IEICE Electron. Express. 8(16), 1343–1347 (2011)

    Google Scholar 

  22. I-Y. Chug, J. Shin, New charge pump circuits for high output and large current drivability. IEICE Electron. Express. 6(12), 800–805 (2009)

    Google Scholar 

  23. S.M. Sze, Semiconductor Devices: Physics & Technology, 2nd edn. (Wiley, Inc., 2002)

    Google Scholar 

  24. H. Nicollean, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (Wiley-Inderscience Publication, 1982)

    Google Scholar 

  25. B.G. Streetman, S. Banerjee, Solid State Electronic Devices, 6th edn. (Prentice Hall Publications, 2006)

    Google Scholar 

  26. Keithley 4200-SCS User Manual, (2000)

    Google Scholar 

  27. K. Yang, C. Hu, MOS capacitance measurements for high-leakage thin dielectrics. IEEE Trans. Electron. Devices. 46(7), 1500–1501 (1999)

    Google Scholar 

  28. S.H. Bae, R.J. Hillard, C.S. Oldsen, M.C. Benjamin, S. Thirupapuliyur, N. Ho, P.A. Kraus, Interface trap characterization of alternate gate dielectrics with elastic gate MOS metrology. AIP Conf. Proc. 788, 191–194 (2005)

    Article  Google Scholar 

  29. Joel L. Plawsky. Electrical properties and diffusion (2004), Renslaesser Institute of Polytechnic. Available: http://homepages.rpi.edu [Online]. (Mar 2004)

  30. Y. W. Park, J. Lee, Device considerations of planar NAND flash memory for extending towards sub-20 nm regime. Proc. IEEE Int. Mem. Workshop. 1–4 (2013)

    Google Scholar 

  31. C-Y. Lu, T-C. Lu, R. Liu, Non-volatile memory technology- today and tomorrow. Proc. IEEE Int. Symp. Phys. Fail. Anal. Integr. Circ. 1, 18–23 (2006)

    Google Scholar 

  32. W.R. Thurber, R.L. Mattis, Y.M. Liu, J.J. Filliben, The Relationship Between Resistivity and Dopant Density for Phosphorus-and Boron-Doped Silicon. (National Bureau of Standards Special Publication, 1981, pp. 400–464)

    Google Scholar 

  33. Synopsys Sentaurus TCAD User Manuals, Version E-2012, Dec 2012

    Google Scholar 

  34. B. Rong, Capacitance-voltage characterization for MOS capacitor on p-type high resistivity silicon substrate. Proc. IEEE Int. Conf. Solid State Integr. Circ. Technol. 1, 198–201 (2004)

    Google Scholar 

  35. H. Hanafi, S. Tiwari, Imran Khan, Fast and long-retention time nano-crystal memory. IEEE Trans. Electron Devices. 43(9), 1553–1558 (1996)

    Google Scholar 

  36. D. Demaria, E. Cartier, Mechanism for stress-induced leakage currents in thin silicon dioxide films. JAP. 78(6), 3883–3894 (1995)

    Google Scholar 

Download references

Acknowledgements

This device was fabricated and characterized at IIT Bombay Nano-Fabrication Centre (IITB-NF), Mumbai, India.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Rasika Dhavse .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Dhavse, R., Prashant, K., Dabhi, C., Darji, A., Patrikar, R.M. (2018). Fabrication and Investigation of Low-Voltage Programmable Flash Memory Gate Stack. In: Nath, V. (eds) Proceedings of the International Conference on Microelectronics, Computing & Communication Systems. Lecture Notes in Electrical Engineering, vol 453. Springer, Singapore. https://doi.org/10.1007/978-981-10-5565-2_4

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-5565-2_4

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-5564-5

  • Online ISBN: 978-981-10-5565-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics