Design of DA-Based FIR Filter Architectures Using LUT Reduction Techniques

  • A. UmaEmail author
  • P. Kalpana
  • T. Naveen Kumar
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 453)


The multiplier-less techniques such as distributed arithmetic (DA) have gained large popularity for its high-speed processing. Architectures based on DA results in cost-efficient and area-efficient structures. This paper presents design and realization of various DA-based FIR filter architectures based on LUT reduction techniques of length N = 4 and also implemented using both shift accumulators and carry save shift accumulators. The larger LUT is subdivided into a number of LUTs to reduce the size of the LUT for higher order filter. FIR filter architectures designed include filter with LUT size of 2 N  − 1 words, filter with LUT size of 2 N − 1 words, filter with LUT breakup contains two 2 N/2 − 1 word LUTs, and also LUT-less filter but only has combinational blocks. These filter architectures have been synthesized for the target FPGA device and results are compared based on RTL area, device utilization, maximum operating frequency, and power consumption.


Distributed arithmetic (DA) Carry save shift accumulator (CSSA) Shift accumulation (SA) 


  1. 1.
    J. Xie, J. He, G. Tan, FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. Micro Electron. J. 365–370 (2010)Google Scholar
  2. 2.
    Y.-H. Chen, J.-N. Chen, T.-Y. Chang, C-W. Lu, High-throughput multistandard transform core supporting MPEG/H.264/VC-1 using common sharing distributed arithmetic. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 22(3), Mar 2014Google Scholar
  3. 3.
    J. Xie, P.K. Meher, J. He, Hardware-efficient realization of prime-length DCT based on distributed arithmetic. IEEE Trans. Comput. 62(6), June 2013Google Scholar
  4. 4.
    D.J. Allred, H. Yoo, V. Krishnan, W. Huang, D.V. Anderson, LMS adaptive filters using distributed arithmetic for high throughput. IEEE Trans. Circ. Syst. I Reg. Pap. 52(7), 1327–1337 (2005)CrossRefGoogle Scholar
  5. 5.
    M.S. Prakash, R.A. Shaik, Low-area and high-throughput architecture for an adaptive filter using distributed arithmetic. IEEE Trans. Circ. Syst. Ii Express Briefs 60(11), Nov 2013Google Scholar
  6. 6.
    S.Y. Park, P.K. Meher, Low-power, high-throughput, and low-area adaptive FIR filter based on distributed arithmetic. IEEE Trans. Circ. Syst. II Express Briefs 60(6), June 2013Google Scholar
  7. 7.
    R. Guo, L.S. DeBrunner, Two high-performance adaptive filter implementation schemes using distributed arithmetic. IEEE Trans. Circ. Syst. Ii Express Briefs 58(9), Sept 2011Google Scholar
  8. 8.
    E. Özalevli, W. Huang, P.E. Hasler, D.V. Anderson, A reconfigurable mixed-signal VLSI implementation of distributed arithmetic used for finite-impulse response filtering. IEEE Trans. Circ. Syst. I Regul. Pap. 55(2), Mar 2008Google Scholar
  9. 9.
    B.K. Mohanty, P.K. Meher, A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm. IEEE Trans. Sig. Process. 61(4), 15 Feb 2013Google Scholar
  10. 10.
    S.Y. Park, P.K. Meher, Efficient FPGA and ASIC realizations of DA-based reconfigurable FIR digital filter. IEEE Trans. Circ. Syst. Ii Express Briefs doi: 10.1109/TCSII.2014.2324418

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of ECEPSG College of TechnologyCoimbatoreIndia

Personalised recommendations