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Design of DA-Based FIR Filter Architectures Using LUT Reduction Techniques

  • A. Uma
  • P. Kalpana
  • T. Naveen Kumar
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 453)

Abstract

The multiplier-less techniques such as distributed arithmetic (DA) have gained large popularity for its high-speed processing. Architectures based on DA results in cost-efficient and area-efficient structures. This paper presents design and realization of various DA-based FIR filter architectures based on LUT reduction techniques of length N = 4 and also implemented using both shift accumulators and carry save shift accumulators. The larger LUT is subdivided into a number of LUTs to reduce the size of the LUT for higher order filter. FIR filter architectures designed include filter with LUT size of 2 N  − 1 words, filter with LUT size of 2 N − 1 words, filter with LUT breakup contains two 2 N/2 − 1 word LUTs, and also LUT-less filter but only has combinational blocks. These filter architectures have been synthesized for the target FPGA device and results are compared based on RTL area, device utilization, maximum operating frequency, and power consumption.

Keywords

Distributed arithmetic (DA) Carry save shift accumulator (CSSA) Shift accumulation (SA) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of ECEPSG College of TechnologyCoimbatoreIndia

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