Balanced Wrapper Design to Test the Embedded Core Partitioned into Multiple Layer for 3D SOC Targeting Power and Number of TSVs

  • Niranjan RajEmail author
  • Indranil Sen Gupta
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 453)


Manufacturing of three-dimensional (3D) IC chips is become executable nowadays with the furtherance in fabrication engineering. However, the process of designing and testing of tools in this regards are even if non-autumnal. One of the main challenges is to reduce the total time for testing of such chips. In order to make a reduction in the test application time, the wrapper design must be balanced such that all scan chain lengths are almost of equal length. Minimization of the scan test time is possible with the help of above-proposed work with the available numeral of through silicon vias (TSVs). The Verilog coding intended for the proposed implementation has been done using Cadence tool to analyze power and delay.


Scan chain Wrapper 3D IC Test access mechanism TSV 


  1. 1.
    C. Giri, S.K. Roy, B. Banerjee, H. Rahaman, Scan Chain Design Targeting Power and Delay Optimization for 3D Integrated Circuits, in Proceedings of IEEE International Conference on Advances in Computing, Control, and Telecommunication Technologies, India (2009), pp. 845–849Google Scholar
  2. 2.
    C. Giri, S.K. Roy, B. Banerjee, H. Rahaman, Test wrapper design for 3D system-on-chip using optimized number of TSVs, International Symposium on Electronic System Design(ISED) (2010), pp. 197–202Google Scholar
  3. 3.
    X. Wu, Y. Chen, K. Chakrabarty, Y. Xie, Test Access Mechanism Optimization for Core-based Three-dimensional SOCs, in IEEE International Conference on Computer Design (2008), pp. 212–218Google Scholar
  4. 4.
    S.K. Goel, E.J. Marinissen, “SOC test architecture design for efficient utilization of test bandwidth”, ACM Trans. Des. Autom. Electron. Syst. 8(4), 399–429 (2003)CrossRefGoogle Scholar
  5. 5.
    B. Noia, K. Chakrabarty, Y. Xie, Test Wrapper Optimization for Embedded Cores in TSV-based Three Dimensional SOCs, in IEEE International Conference on Computer Design (2009), pp 70–77Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics & Communication EngineeringNational Institute of TechnologyShillongIndia
  2. 2.Department of Computer Science & EngineeringIndian Institute of TechnologyKharagpurIndia

Personalised recommendations