Abstract
Manufacturing of three-dimensional (3D) IC chips is become executable nowadays with the furtherance in fabrication engineering. However, the process of designing and testing of tools in this regards are even if non-autumnal. One of the main challenges is to reduce the total time for testing of such chips. In order to make a reduction in the test application time, the wrapper design must be balanced such that all scan chain lengths are almost of equal length. Minimization of the scan test time is possible with the help of above-proposed work with the available numeral of through silicon vias (TSVs). The Verilog coding intended for the proposed implementation has been done using Cadence tool to analyze power and delay.
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References
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Raj, N., Gupta, I.S. (2018). Balanced Wrapper Design to Test the Embedded Core Partitioned into Multiple Layer for 3D SOC Targeting Power and Number of TSVs. In: Nath, V. (eds) Proceedings of the International Conference on Microelectronics, Computing & Communication Systems. Lecture Notes in Electrical Engineering, vol 453. Springer, Singapore. https://doi.org/10.1007/978-981-10-5565-2_10
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DOI: https://doi.org/10.1007/978-981-10-5565-2_10
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