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Information and Communication Technology pp 113–122Cite as

Restricted Turn Model Fault Tolerant Routing Techniques for 3D Mesh Network-on-Chip: An Evaluation

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Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 625))

Abstract

Communication plays a crucial role in design and performance of multi-core system-on-chips (SoCs). Recent development in nanoscale has opened an alternative option to conventional on-chip communication network with uniform stackable multi-chip modules in three dimensions. As the feature size continues to shrink, transient failures or permanent physical damages of on-chip network links are becoming a critical issue. To overcome these failures, network-on-chip (NoC) routing scheme can be enhanced by adding fault tolerant capabilities. In this paper, we analyze the performance of restricted turn model-based routing for the 3D mesh NoC, namely partially adaptive fault tolerant odd even (FTOE3D) routing, fault tolerant negative first (FTNF3D) routing, and fault tolerant XYZ (FTXYZ) routing. As compared to other two routing algorithms, FTOE3D gives the promising results. This document is in the required format.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Malaviya National Institute of Technology Jaipur, Jaipur, India

    Ravindra Kumar Saini & Mushtaq Ahmed

Authors
  1. Ravindra Kumar Saini
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  2. Mushtaq Ahmed
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Correspondence to Ravindra Kumar Saini .

Editor information

Editors and Affiliations

  1. Microsoft Innovation Centre, Sri Aurobindo Institute of Technology Microsoft Innovation Centre, Indore, Madhya Pradesh, India

    Durgesh Kumar Mishra

  2. Faculty of Computers and Information, Banha University Faculty of Computers and Information, Banha, Egypt

    Ahmad Taher Azar

  3. Sabar Institute of Technology, Asst. Prof., Dept. of Info. Tech. Sabar Institute of Technology, Gujarat, Gujarat, India

    Amit Joshi

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Saini, R.K., Ahmed, M. (2018). Restricted Turn Model Fault Tolerant Routing Techniques for 3D Mesh Network-on-Chip: An Evaluation. In: Mishra, D., Azar, A., Joshi, A. (eds) Information and Communication Technology . Advances in Intelligent Systems and Computing, vol 625. Springer, Singapore. https://doi.org/10.1007/978-981-10-5508-9_10

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  • DOI: https://doi.org/10.1007/978-981-10-5508-9_10

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-5507-2

  • Online ISBN: 978-981-10-5508-9

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