Block-Random Access Memory-Based Digital Pulse Modulator Architecture for DC–DC Converters

Abstract

This paper proposes a new digital pulse-width modulation (DPWM) and digital frequency modulation (DPFM) architecture using block RAM (BRAM) present in the field-programmable gate arrays (FPGAs). In Xilinx FPGAs, Block RAM (BRAM) elements are available only with a synchronous reset. As the synchronous reset is used in this code, the synthesis tool implemented the code in a single BRAM element. This minimizes the decoding logic and reduces the area. Block RAM available in FPGA is used to store the desired pattern to derive the variable duty cycle and variable-frequency pulses. This DPWM/DPFM architecture can be used with switching type of DC–DC converters under both light- and heavy-load conditions. Architecture is developed with Verilog hardware language for three different control bits (4 bit, 5 bit, and 6 bit), synthesized, and implemented with Xilinx PlanAhead 14.2 tool. This proposed architecture provides higher resolution without any requirement for higher clock frequency and larger logic resources which ultimately wits the small change in output voltage produced at the output of power converter. Maximum operating frequency of 306 MHz can be achieved for 4-bit control input. For the 6-bit control input, 4096 different bit patterns are stored to derive the more precise pulses to control the DC–DC converters.