Skip to main content

Triple Gate SOI MOSFET

  • Conference paper
  • First Online:
  • 1907 Accesses

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 443))

Abstract

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) had been one of the best devices designed for integrated circuits over the decades. Due to continuous downscaling of the transistor the short-channel effects comes into play and further scaling becomes difficult. So, Multi-gate devices have been proposed so as to reduce these effects. Analytical modeling of Tri-gate MOSFET by solving Poisson’s equation and necessary boundary condition is proposed in this paper. Surface potential for Tri-gate SOI MOSFET has been obtained and the effects of the device parameters like oxide thickness, different oxide material, channel length, gate voltage and drain voltage are plotted using MATLAB simulator.

This is a preview of subscription content, log in via an institution.

References

  1. Moore, G.E.: Cramming more components onto the integrated circuits. (Reprinted from Electronics, pp. 114–117, April 19, 1965). Proc. IEEE 86, 82–85 (1998)

    Google Scholar 

  2. Semiconductor Industry Association. International technology roadmap for semiconductors (2000 update)

    Google Scholar 

  3. Bohr, M.: A 30 year retrospective on Dennard’s MOSFET scaling paper. IEEE Solid-State Circ. Soci. 9, 11–15 (2007)

    Google Scholar 

  4. Taur, Y., Buchanan, D.A., Chen, W., Frank, D.J., Ismail, K.E., Lo, S.H., SaiHalasz, G.A., Viswanathan, R.G., Wann, H.J.C., Wind, S.J., Wong, H.S.: CMOS scaling into the nanometer regime. Proc. IEEE 85, 486–504 (1997)

    Article  Google Scholar 

  5. Young, K.K.: Short-channel effects in fully depleted SOI MOSFET’s. IEEE Trans. Electron Devices 36, 399–402 (1989)

    Article  Google Scholar 

  6. Fischetti, M.V., Laux, S.E., Crabbe, E.: Understanding hot-electron transport in silicon devices—is there a shortcut. J. Appl. Phys. 78, 1058–1087 (1995)

    Article  Google Scholar 

  7. Ning, T.H., Osburn, C.M., Yu, H.N.: Emission probability of hot electrons from silicon into silicon dioxide. J. Appl. Phys. 48, 286–290 (1997)

    Article  Google Scholar 

  8. Zhang, Q., Zhao, W.: Low subthreshold swing tunnel transistors. IEEE Trans. Device Lett. 27, 297–300 (2006)

    Article  Google Scholar 

  9. Banna, S.R., Chan, P.C.H., Ko, P.K., Nguyen, C.T., Chan, M.: Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET’s. IEEE Trans. Electron. Devices 42, 1949–1955 (1995)

    Article  Google Scholar 

  10. Garduño, S.I., Cerdeira, A., Estrada, M., Alvarado, J., Kilchystka, C., Flandre, D.: Contribution of the carrier tunnelling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field effect transistor. J. Appl. Phys. 109, 1–7 (2011)

    Article  Google Scholar 

  11. Liu, Z.H.: Threshold voltage model for deep submicrometer MOSFETs. IEEE Trans. Electron. Devices 40, 86–90 (1993)

    Article  Google Scholar 

  12. Colinge, J.: The new generation of SOI MOSFETs. Rom. J. Inf. Sci. Techno. 111, 3–15 (2008)

    Google Scholar 

  13. Park, J.T., Colinge, J.P.: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans. Electron. Devices 49, 2222–2229 (2002)

    Article  Google Scholar 

  14. LuD, D., Dunga, M.V., Lin, C.H., Niknejad, A.M., HuC.: A multi-gate MOSFET compact model featuring independent-gate operation. IEDM (2007)

    Google Scholar 

  15. Chaudhry, A., Kumar, M.J.: Controlling short-channel effects in deep submicron SOI MOSFET’s for improved reliability: a review. IEEE Trans. Device Mater. Rel. 4, 99–109 (2004)

    Article  Google Scholar 

  16. Lemme, M., Mollenhauer, T., Henschel, W., Wahlbrink, T., Gottlob, H., Favi, J., Baus, M., Winkler, O., Spangenberg, B., Kurz, H.: Subthreshold behavior of triple-gate MOSFETs on SOI Material. Solid State Electron. Lett. 48, 529–534 (2003)

    Article  Google Scholar 

  17. Doyle, B., Boyanov, B.: Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout. In: Digest of Technical Papers, Symposium on VLSI Technology, USA (2003)

    Google Scholar 

  18. Suzuki, K., Pidin, S.: Short-channel single-gate SOI MOSFET model. IEEE Trans. Electron. Devices 50, 1297–1305 (2003)

    Article  Google Scholar 

  19. Mohammadi, H., Abdullah, H., Fu, Dee C.: A review on modeling the channel potentialin multi-gate MOSFETs. Sains Malaysiana Publ. 43, 861–866 (2014)

    Google Scholar 

  20. Frank, D.J., Taur, Y.: Generalized scale length for two-dimensional effects in MOSFETs. Electron. Device Lett. IEEE 19, 385–387 (1998)

    Article  Google Scholar 

  21. Auth, C.P., Plummer, J.D.: A simple model for threshold voltage of surrounding-gate MOSFET’s. IEEE Trans. Electron. Devices 45, 2381–2383 (1998)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Amit Agarwal .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Agarwal, A., Pradhan, P.C., Swain, B.P. (2018). Triple Gate SOI MOSFET. In: Kalam, A., Das, S., Sharma, K. (eds) Advances in Electronics, Communication and Computing. Lecture Notes in Electrical Engineering, vol 443. Springer, Singapore. https://doi.org/10.1007/978-981-10-4765-7_12

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-4765-7_12

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-4764-0

  • Online ISBN: 978-981-10-4765-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics