Skip to main content
SpringerLink
Log in
Book cover

Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications pp 239–246Cite as

Novel Design of Pulse Trigger Flip-Flop with High Speed and Power Efficiency

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 434))

Abstract

In flip-flops (FF) it is considered that about 50% of the total power is consumed by clock distribution or the associated memory. Hence, there is a demand for design of FF with low power rating. Several designs are proposed to achieve this. In this paper, a pulse triggered scheme is adopted in order to reduce the power consumption. This typically helps to reduce the long discharging path. The proposed pulse trigger FF in this chapter is realized using transmission gate-based signal feed through scheme. This will increase the signal feed through capabilities and capable of driving large loads. The post-layout simulation carried out for the layout drawn at CMOS 90 nm and the results were compared with the conventional P-FF design.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Kawaguchi. H., Sakurai. T.: A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE Journal of Solid-State Circuit, vol. 33, no. 5, pp. 807–811, (May, 1998)

    Google Scholar 

  2. Chen. K.: A 77% energy saving 22-transistor single phase clocking D-Flip flop with adoptive-coupling configuration in 40-nm CMOS. in IEEE International Solid State Circuits Conference, (Nov, 2011)

    Google Scholar 

  3. Consoli. E., Alioto. M., Palumbo. G., Rabaey. J.: Conditional Push-pull pulsed latch with 726 flops energy delay product in 65 nm CMOS. in IEEE International Solid State Circuits Conference, (Feb, 2012)

    Google Scholar 

  4. Sadrossadat. S., Mostafa., H., Anis. M.: Statistical design framework of sub-micron flip-flop circuits considering die-to-die and within -die variations. IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 2, pp. 69–79, (Feb, 2011)

    Google Scholar 

  5. Alioto. M., Consoli. E., Palumbo. G.: General strategies to design nanometer flip-flops in the energy-delay space. IEEE Transactions on Circuits and Systems, vol. 57, no. 7, pp. 1583–1597, (Jul, 2010)

    Google Scholar 

  6. Alioto. M., Consoli. E., Palumbo. G.: Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: PART-II—results and Fig..s of merit. IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 5, pp. 737–750, (May, 2011)

    Google Scholar 

  7. Sadrossadat. S., Mostafa. H., Anis. M.: Statistical design framework of sub-micron lip-flop circuits considering die-to-die and within-die variations. IEEE Transactions on Semi-conductor manufacturing, vol. 24, no. 2, pp. 69–79, (Feb, 2011)

    Google Scholar 

  8. B. Kong, S. KIm and Y. Jun, “Conditional-capture flip-flop for statistical power reduction. IEEE journal for Solid State Circuits, vol. 36, no. 8, pp. 1263–1271, (Aug, 2001)

    Google Scholar 

  9. H. Y-T., L. j-f., S. M.H.: Low power pulse triggered flip-flop design with conditional pulse enhancement scheme. IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 20, no. 2, pp. 361–366, (Feb, 2012)

    Google Scholar 

  10. Zhao. P., Darwish. T., Bayoumi, M.: High-performance and low. IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 12, no. 5, pp. 477–484, (May, 2004)

    Google Scholar 

  11. P. M.W., G. W-L., Y. K-S.: A low-power static dual edge triggered flip-flop using an output-controlled discharge configuration. in IEEE International symposium on Circuits and Systems, (May, 2005)

    Google Scholar 

  12. Jin-Fa. L.: Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 1, pp. 181–185, (Jan, 2014)

    Google Scholar 

  13. Zhao. P., McNeely. J., Venigalla. S., Kumar. GP. P., Bayoum. M., Wang. N., Downey. L.: Clocked-pseudo-NMOS flip-flops for level conversion in dual supply systems. IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 17, no. 9, pp. 1196–1202, (Sep, 2009)

    Google Scholar 

  14. Rasouli. S. H., Khademzadeh. A., Afzali-kusha. A., Nourani. M.: Low power single- and double-edge-triggered flip-flops for high speed application,” in IEEE Circuits Devices & Systems, (Apr, 2005)

    Google Scholar 

  15. Mahmoodi. H., Tirumalashetty. V., Cooke. M., Roy. K.: Ultra low power clocking scheme using energy recovery and clock gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 1, pp. 33–44, (Jan, 2009)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of ECE, Lendi Institute of Engineering & Technology, Jonnada, Vizianagaram, Andhra Pradesh, India

    Satish Kotta & Rajanbabu Mallavarapu

Authors
  1. Satish Kotta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rajanbabu Mallavarapu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Satish Kotta .

Editor information

Editors and Affiliations

  1. Deparment of Computer Science and Engineering, PVP Siddhartha Institute of Technology, Vijayawada, Andhra Pradesh, India

    Suresh Chandra Satapathy

  2. Department of Electronics and Communication Engineering, Shri Ramswaroop Memorial Group, Lucknow, Uttar Pradesh, India

    Vikrant Bhateja

  3. Department of ECE, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India

    P. Satish Rama Chowdary

  4. Department of ECE, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India

    V.V.S.S. Sameer Chakravarthy

  5. Department of Electronics and Telecommunications, Universitat Ramon Llull, Barcelona, Barcelona, Spain

    Jaume Anguera

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this paper

Cite this paper

Kotta, S., Mallavarapu, R. (2018). Novel Design of Pulse Trigger Flip-Flop with High Speed and Power Efficiency. In: Satapathy, S., Bhateja, V., Chowdary, P., Chakravarthy, V., Anguera, J. (eds) Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 434. Springer, Singapore. https://doi.org/10.1007/978-981-10-4280-5_25

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-4280-5_25

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-4279-9

  • Online ISBN: 978-981-10-4280-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation