Abstract
Interconnects are integral part in the chip design which are responsible for the flow of signal from input to output. Due to the presence of parasitic such as resistance, capacitance components, and intermediate devices, the signal integrity problems may occur. Nowadays, because of technological advances, the effects of parasitic are increasing, which are causing adverse effect on the circuit performance in terms of delay and power. So interconnects have become a major problem. In this paper an endeavor has been made to simulate and examine the effect of interconnects due to variation of line parasitic on the circuit performance parameters in various DSM technologies. Here the values of R and C have been estimated for copper interconnects in different technologies with variable lengths and developed a simple RC interconnect simulation model with a driver and load concepts. For the simulated interconnect model with different interconnect structures and variable lengths, delay and PDP values are estimated. Within the same technology, the simulation results of performance metrics indicate 10% variations for variable lengths of interconnects, 5% variation with different interconnect structures, and more than 50% variation in different technologies.
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Venkataiah, C., Satyaprasad, K., Jaya Chandra Prasad, T. (2018). Effect of Line Parasitic Variations on Delay and Energy of Global On-Chip VLSI Interconnects in DSM Technology. In: Satapathy, S., Bhateja, V., Chowdary, P., Chakravarthy, V., Anguera, J. (eds) Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 434. Springer, Singapore. https://doi.org/10.1007/978-981-10-4280-5_23
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DOI: https://doi.org/10.1007/978-981-10-4280-5_23
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