Abstract
The usage of digital devices is increasing rapidly and they became essential part of everyone’s life. Digital devices can be designed according to their application and most of them are realized using arithmetic processor which consists of several operations like addition, subtraction, multiplication, etc., all of them can be implemented using full adder as the basic building block. As full adder plays a major role in digital devices we need to design a low-power full adder such that the devices can operate at lower power consumption and has longer battery life. In this research work, a hybrid low-power 1-bit full adder was designed using CMOS logic, pass transistor, and transmission gate logic with 14 transistor. The design was simulated using HSPICE tools in 90 nm technology with supply voltage of 1.2 V. Performance parameters, such as power, delay, and power delay product were compared with the existing designs, such as C-CMOS Full Adder, Mirror adder, hybrid pass-logic with static CMOS output drive full adder and found that the proposed adder has the low-power consumption and power delay product than the aforementioned adders.
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Mannepalli, C., Kommu, C. (2018). Modified Low-Power Hybrid 1-Bit Full Adder. In: Satapathy, S., Bhateja, V., Chowdary, P., Chakravarthy, V., Anguera, J. (eds) Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 434. Springer, Singapore. https://doi.org/10.1007/978-981-10-4280-5_20
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DOI: https://doi.org/10.1007/978-981-10-4280-5_20
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