Advertisement

Design of CMOS Integrator Circuit for Sigma Delta ADC for Aerospace Application

  • Deepak PrasadEmail author
  • Vijay Nath
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 11)

Abstract

In this research paper, a design of CMOS integrator circuit for sigma delta ADC has been carried out. The proposed integrator claims a key role in low-power CMOS sigma delta ADC. The low-power CMOS sigma delta ADC is used to design smart temperature sensor for aerospace application which would sense a temperature range of −50 to 150 °C. The analog output of temperature sensor is digitized using low power CMOS sigma delta ADC. The integrator behaves as a low-pass filter for input signal and high-pass filter for quantization noise. Here, the input and output are measured across the capacitor. This circuit is designed using Cadence Virtuoso UMC90 nm CMOS technology. For the proper operation of the circuit, power supply is used in the range of +1.3 to −1.3 V. As the input square wave is applied, during the positive half cycle, the voltage across capacitor increases from zero to the maximum (peak value of applied voltage). During the negative half cycle, the capacitor starts to discharge and comes to zero.

Keywords

Integrator Sigma delta ADC Capacitor Resistor 

Notes

Acknowledgements

We are thankful to RESPOND ISRO, Bangalore for funding this research work. We are also thankful to Prof. V. R. Gupta, HOD ECE, Prof. T. Ghosh, Dean (SR), and Prof. R. Sukesh Kumar, Dean (FA) & Prof. M.K. Mishra, Vice chancellor, BIT Mesra Ranchi for providing infrastructure facility to carry out this research work.

References

  1. 1.
    Allen, P.E., Holberg, D.R.: CMOS Analog Circuit Design. Oxford University Press (2002)Google Scholar
  2. 2.
    Weste, N.H., Eshraghian, K.: Principles of CMOS VLSI Design, vol. 2. Addison Wesley, MA (1993)Google Scholar
  3. 3.
    Kamath, D.V.: Overview of OPAMP and OTA based integrators. Int. J. Innov. Res. Electr. Electron. Instrum Control Eng. 3(9), (2015)Google Scholar
  4. 4.
    Sedra, A., Smith, K.C.: Microelectronic Circuits. Oxford University Press (2004)Google Scholar
  5. 5.
    Shem, B., Kozak, M., Friedman, G.: A high-speed CMOS op-amp design technique using negative miller capacitance. In: IEEE (2004)Google Scholar
  6. 6.
    Mandal, P., Visvanathan, V.: A new approach for CMOS op-amp synthesis. In: VLSI Design, Twelfth International Conference (1999)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.VLSI Design Group, Department of ECEBirla Institute of TechnologyRanchiIndia

Personalised recommendations