Abstract
Coarse-Grained Reconfigurable Architecture (CGRA) is currently receiving attention as it is a strong emerging class with excellent performance as well as flexibility in fabrication. System building blocks uses the entire range of components is available as choices for. The Reconfigurable fabric (RF) will be offered as an important building block for complex system design, CGRA processor. This paper gives an innovative design of reconfigurable fabric (RF) performing with parallel processing techniques. Cryptographic hash function is a hash function which cannot be inverted practically, to regenerate the input data from its hash value alone. RF having 16 processing elements (PE) in mesh-type topology for single dimensional processing of encryption technique. The analyzing parameters for this design are power, processing speed and area on various FPGAs.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
“High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures”, Amupam Chattopadhyay, Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10–14, 2008
Hyunchul Park, Kevin Fan, “Modulo Graph Embedding: Mapping Applications onto Coarse Grained Reconfigurable Architectures”, Proceedings of the 2006 - dl.acm.org/
“Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture”, Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 5, MAY 2009
“Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture”, Yoonjin Kim, , Rabi N. Mahapatra, Ilhyun Park, IEEE, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 10, OCTOBER 2010
“A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors” Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 10, OCTOBER 2008
“Reducing Control Power in CGRAs with Token Flow”, Hyunchul Park, Yongjun Park, and Scott Mahlke, DATE 2008
Allan Carroll, Stephen Friedman, “Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency”, proceeding 8 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, pages 161–170
“A Coarse Grained Reconfigurable Architecture Framework supporting Macro-Dataflow Execution”, thesis submitted Keshavan Varadarajan, december 2012 at IIS, Bangalore
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Khorgade, M., Dakhole, P. (2017). Analysis of Reconfigurable Fabric Architecture with Cryptographic Application Using Hashing Techniques. In: Patnaik, S., Popentiu-Vladicescu, F. (eds) Recent Developments in Intelligent Computing, Communication and Devices. Advances in Intelligent Systems and Computing, vol 555. Springer, Singapore. https://doi.org/10.1007/978-981-10-3779-5_11
Download citation
DOI: https://doi.org/10.1007/978-981-10-3779-5_11
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-3778-8
Online ISBN: 978-981-10-3779-5
eBook Packages: EngineeringEngineering (R0)