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Implementation of Low-Power 6T SRAM Cell Using MTCMOS Technique

  • Tripti TripathiEmail author
  • D. S. Chauhan
  • S. K. Singh
  • S. V. Singh
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 553)

Abstract

Electronics industry in present-day scenario is facing the major problem of standby leakage current in most of the electronic devices. As the speed of processor is increasing, the demand for high-speed cache memory is ever increasing. SRAM being mainly used for cache memory design, several low-power techniques are being used to reduce its leakage current. Full CMOS 6T SRAM cell is the most preferred choice for most of the digital circuits. This paper implements 6T CMOS SRAM cell using MTCMOS technique and simulation results show significant reduction in leakage during standby mode. The simulations are done on Cadence Virtuoso Tool using 45 nm technology.

Keywords

CMOS SRAM Sub-threshold leakage 

References

  1. 1.
    Andrea Calimera et al., ‘Design techniques and architectures for low leakage SRAMs’, IEEE transactions on circuits and systems, vol. 59, No. 9, pp. 1992–2007, Sept. 2012.Google Scholar
  2. 2.
    ‘International technical roadmap for semiconductors’, 2009 available online at http:// www.itrs.net/links/ 2009ITRS/home2009.htm
  3. 3.
    Li-Jun Zhang et al., ‘Leakage power reduction techniques of 55 nm SRAM cells’, IETE Technical Review, Vol. 22, issue 2, pp. 135–145, 2001.Google Scholar
  4. 4.
    Debasis Mukherjee et al., ‘Static noise margin analysis of SRAM cell for high speed application’, International Journal of Computer Science Issues, Vol. 7, Issue 5, 2010Google Scholar
  5. 5.
    G. Razavipour et al., ‘Design and Analysis of Two Low-Power SRAM Cell Structures’, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, pp. 1551–1555, Oct. 2009.Google Scholar
  6. 6.
    S. Shigematsu et al., ‘A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits’, IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, June 1997Google Scholar
  7. 7.
    B. Amelifard et al., ‘Leakage minimization of SRAM cells in a dual-Vt and dual-Tox technology’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 851–859, July 2008.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • Tripti Tripathi
    • 1
    Email author
  • D. S. Chauhan
    • 2
  • S. K. Singh
    • 3
  • S. V. Singh
    • 4
  1. 1.Inderprastha Engineering CollegeGhaziabadIndia
  2. 2.GLA UniversityMathuraIndia
  3. 3.VIETGhaziabadIndia
  4. 4.JIITNoidaIndia

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