Abstract
Synchronous programming models capture concurrency in computation quite naturally, especially in its dataflow multi-clock flavor. With the rising importance of multi-clock in safety-critical embedded systems, there is a growing need for model driven synthesizing simulation of such systems. This paper proposes an approach to simulate the dataflow behaviors of multi-clock system designed in SIGNAL as a feedback for the system designer.
We address it by transforming the clock relations from the original system into MARTE time model specified by CCSL. The formal operational semantics of CCSL makes it executable. Then we can produce a visible simulation of the system dataflow, even adding the information of candidate execution platform. A case-study is showed to illustrate our work, the original system is a multi-clock system which is designed in SIGNAL. We detect the dataflow latency through our approach. Then we give a more exhaustive simulation by allocate the platform into the system.
This work was supported by the National High-tech R&D Program of China (863 Program) under Grant No. 2015AA015303; “Project 61272083 supported by National Natural Science Foundation of China”; Fundamental Research Funds for the Central Universities (NS2015093); Supported by National key research and development program 2016YFB1000802.
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Wang, Z., Shen, G., Huang, Z., Si, J., Pan, C. (2016). A Simulation Approach for SIGNAL Time Model Concern on Multi-clock System. In: Zhang, L., Xu, C. (eds) Software Engineering and Methodology for Emerging Domains. NASAC 2016. Communications in Computer and Information Science, vol 675. Springer, Singapore. https://doi.org/10.1007/978-981-10-3482-4_3
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