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International Conference on Smart Trends for Information Technology and Computer Communications

SmartCom 2016: Smart Trends in Information Technology and Computer Communications pp 27–38Cite as

Nano Scale Dual Material Gate Silicon on Nothing Junctionless MOSFET for Improving Short Channel Effect and Analog Performance

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Part of the book series: Communications in Computer and Information Science ((CCIS,volume 628))

Abstract

Silicon-on-insulator (SOI) suffers with various drawbacks so Silicon-on-nothing (SON) has been the researchers recent target. The result shows that surface potential and electric field is maximum compare to Single Material Gate as well as Dual Material Gate SOI junctionless Transistor (DMG SOI JLT). Various targeted features comprise such as maximum on-state current, improved transconductance Gm, Gm/IDS and reduced drain induced barrier lowering. In this paper is the work on the parametric effect of two layer gate stack (DGS) (High dielectric/Sio2) on the Dual Material Gate (DMG) for SON Junctionless Transistor. The results obtained by the simulation for 40 nm channel length with work function as 4.77 and 4.1 eV with doping concentration (0.4 × 1018 cm−3).

Y.V. Chavan—Sr IEEE-Member

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Author information

Authors and Affiliations

  1. Department of Electronics and Telecommunication, JSPM’s RSCOE, Tathawade, Pune, India

    S. C. Wagaj & Y. V. Chavan

  2. Savitribai Phule Pune University, Pune, India

    S. C. Wagaj & Y. V. Chavan

Authors
  1. S. C. Wagaj
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  2. Y. V. Chavan
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Corresponding author

Correspondence to S. C. Wagaj .

Editor information

Editors and Affiliations

  1. Stanford University, Stanford, CA, USA

    Aynur Unal

  2. IT Buzz Limited, Dagenham, UK

    Malaya Nayak

  3. Microsoft Innovation Centre, Sri Aurobindo Institute of Technology, Indore, Madhya Pradesh, India

    Durgesh Kumar Mishra

  4. Namibia University of Science and Technology, Windhoek, Namibia

    Dharm Singh

  5. Sabar Institute of Technology, Sabarkantha, India

    Amit Joshi

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© 2016 Springer Nature Singapore Pte Ltd.

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Wagaj, S.C., Chavan, Y.V. (2016). Nano Scale Dual Material Gate Silicon on Nothing Junctionless MOSFET for Improving Short Channel Effect and Analog Performance. In: Unal, A., Nayak, M., Mishra, D.K., Singh, D., Joshi, A. (eds) Smart Trends in Information Technology and Computer Communications. SmartCom 2016. Communications in Computer and Information Science, vol 628. Springer, Singapore. https://doi.org/10.1007/978-981-10-3433-6_4

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  • DOI: https://doi.org/10.1007/978-981-10-3433-6_4

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-3432-9

  • Online ISBN: 978-981-10-3433-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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