Abstract
In this paper, a new and novel Reward-Punishment-based Variable Step Size Least Mean Square (RP-VSSLMS) algorithm has been proposed and a novel methodology is used to construct a Rayleigh fading channel adaptive equalizer employing the proposed algorithm in hardware domain. As the Rayleigh fading channel reveals the property of real-time wireless communication environment, it is chosen here. The Spartan 6 FPGA board is configured here to model the digital circuitry of the proposed RP-VSSLMS algorithm using a novel “Hardware Co-simulation” technique. The hardware co-simulation analysis showed that, the proposed RP-VSSLMS algorithm has faster convergence speed, smaller steady-state misadjustment, and lesser computational complexity than the existing LMS and VSSLMS algorithms. The performance of the proposed algorithm is observed by calculating the Bit Error Rate (BER) of different modulated signals under Rayleigh Fading channel.
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Bose, S., Misra, I.S. (2018). FPGA-Based Equalizer Design Using a Novel Adaptive Reward-Punishment VSSLMS Algorithm for Rayleigh Fading Channel. In: Sa, P., Sahoo, M., Murugappan, M., Wu, Y., Majhi, B. (eds) Progress in Intelligent Computing Techniques: Theory, Practice, and Applications. Advances in Intelligent Systems and Computing, vol 719. Springer, Singapore. https://doi.org/10.1007/978-981-10-3376-6_58
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DOI: https://doi.org/10.1007/978-981-10-3376-6_58
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