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Performance Analysis and Implementation of Highly Reconfigurable Modified SDM-Based NoC for MPSoC Platform on Spartan6 FPGA

  • Y. Amar Babu
  • G. M. V. Prasad
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 518)

Abstract

To meet today’s demanding requirements such as low power consumption and high performance while maintaining flexibility and scalability, system-on-chip will integrate several number of processor cores and other IPs with network-on-chip. To implement NoC-based MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time-reconfigurable. Current TDM- and SDM-based NoCs take more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing-based NoC on FPGA; in this we have modified complex network interface and proposed flexible network interface and efficient SDM-based NoC. This proposed architecture explored feasibility of connection requirements dynamically from soft cores during run-time.

Keywords

NoC SDM VHDL code Microblazes 

References

  1. 1.
    International Technology Roadmap for Semiconductors: Semiconductor Industry Association, Dec 2015.Google Scholar
  2. 2.
    K. Goossens, J. Dielissen, and A. Radulescu, “Æthereal network on chip: concepts, architectures, and implementations,” IEEE Design & Test of Computers, vol. 22, pp. 414–21, 2005.Google Scholar
  3. 3.
    E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “QNoC: QoS architecture and design process for network on chip,” Journal of Systems Architecture, vol. 50, pp. 105–128, 2004.Google Scholar
  4. 4.
    C. Hilton and B. Nelson, “PNoC: A flexible circuit-switched NoC for FPGA-based systems,” IEE Proceedings: Computers and Digital Techniques, vol. 153, pp. 181–188, 2006.Google Scholar
  5. 5.
    A. Leroy, D. Milojevic, D. Verkest, F. Robert, and F. Catthoor, “Concepts and implementation of spatial division multiplexing for guaranteed throughput in networks-on-chip,” IEEE Transactions on Computers, vol. 57, pp. 1182–1195, 2008.Google Scholar
  6. 6.
    J. Rose and S. Brown, “Flexibility of interconnection structures for field programmable gate arrays,” IEEE Journal of Solid-State Circuits, vol. 26, pp. 277–282, 1991.Google Scholar
  7. 7.
    A. Kumar, S. Fernando, Y. Ha, B. Mesman, and H. Corporaal, “Multiprocessor system-level synthesis for multiple applications on platform FPGA,” in Proceedings–2007 International Conference on Field Programmable Logic and Applications, FPL, 2007, pp. 92–97.Google Scholar
  8. 8.
    A. Javey, J. Guo, M. Paulsson, Q. Wang, D. Mann, M. Lundstrom, and H. Dai. High-field quasiballistic transport in short carbon nanotubes. Physical Review Letters, 92(10), 2004.Google Scholar
  9. 9.
    V. Agarwal, M. S. Hrishikesh, S.W. Keckler, and D. Burger. Clock rate versus ipc: the end of the road for conventional microarchitectures. In ISCA’00: Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 248.259. ACM.Google Scholar
  10. 10.
    R. H. Havemann, and J. A. Hutchby, “High Performance Interconnects: An Integration Overview”, Proceedings of the IEEE, vol. 89, No. 5, May 2001.Google Scholar
  11. 11.
    D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G. De Micheli, “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 16, pp. 113–129, 2005.Google Scholar
  12. 12.
    T. Bjerregaard and J. Sparso, “A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip,” in Proceedings -Design, Automation and Test in Europe, DATE’05, 2005, pp. 1226–1231.Google Scholar
  13. 13.
    D. Castells-Rufas, J. Joven, and J. Carrabina, “A validation and performance evaluation tool for ProtoNoC,” in 2006 International Symposium on System-on-Chip, SOC, 2006.Google Scholar
  14. 14.
    A. Lines, “Asynchronous interconnect for synchronous SoC design,” IEEE Micro, vol. 24, pp. 32–41, 2004.Google Scholar
  15. 15.
    M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, “Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip,” in Proceedings–Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 890–895.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.LBR College of EngineeringMylavaramIndia
  2. 2.B.V.C Institute of Technology & ScienceBatlapalemIndia

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