Abstract
Power and performance have become significant metrics in the designing of multicore processors. Due to the ceasing of Moore’s law and Dennard scaling, reducing power budget without compromising the overall performance is considered as a predominant limiting factor in multicore architecture. Of late technological advances in power management techniques of the multicore system substantially balance the conflicting goals of low power, low cost, small area, and high performance. This paper aims at ascertaining more competent power management techniques for managing power consumption of multicore processor through investigations. We highlight the necessity of the power management techniques and survey several new approaches to focus their pros and cons. This article is intended to serve the researchers and architects of multicore processors in accumulating ideas about the power management techniques and to incorporate it in near future for more effective fabrications.
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References
Silven, O., Jyrkka, K.: Observations on Power-Efficiency Trends in Mobile Communication Devices. EURASIP J. Embedded Systems, vol. 2007, no. 1, p. 17 (2007).
Gordon E. Moore. Cramming more components onto integrated circuits. vol. 86(1); pp. 82–85, IEEE (1998).
Christian Martin.: Post-Dennard Scaling and the final years of Moore’s Law consequences for the evolution of multicore-architectures. Hochschule Augsburg University of Applied Sciences, Technical Report (2014).
Intel Corp.: Intel core i7-940 processor. Intel Product Information, 2009 [Online]. Available: http://ark.intel.com/cpu.aspx?groupId=37148.
May, D.: XMOS XS1 architecture and XS1 Chips. Micro IEEE; vol. 32(6); pp. 28–37, IEEE (2012).
Advanced Micro Devices Inc.: ATI Radeon HD 4850 & ATI Radeon HD 4870—GPU specifications. AMD Product Information, 2008. [Online] Available: http://ati.amdcom/products/radeonhd4800/specs3.html.
Gschwind, M., Hofstee, H.P., Flachs, B., Hopkin, M., Watanabe, Y., Yamazaki, T.: Synergistic Processing in Cell’s Multicore Architecture, vol. 26(2); pp. 10–24, IEEE (2006).
ARM Ltd.: ARM Development Tools., 2011. [Online] Available: http://www.arm.com/products/tools/development-boards/versatileexpress/index.php.
Pericas, M., Cristal, A., Cazorla, F.J., Gonzalez, R., Jimenez, D.A., Valero, M.: A flexible heterogeneous multi-core architecture. In Proceedings of 16th International Conference on Parallel Architecture and Compilation Techniques, pp. 13–24, IEEE (2007).
Intel 64 and IA-32 Architectures.: Software Developer’s Manual. Intel Developer Manuals, vol.3A, (2008).
Intel Corp.: Intel atom processor for nettop platforms. Intel Product Brief, 2008. [Online]. Available: http://download.intel.com/products/atom/319995.pdf.
Advanced Micro Devices Inc.: Key architectural features—AMD Phenom II processors. AMD Product Information, 2008 [Online]. Available: http://www.amd.com/usen/Processors/ProductInformation/0,301181533115917%5E15919,00.html.
Advanced Micro Devices Inc.: Software optimization guide for AMD family 10 h processors. AMD White Papers and Technical Documents, Nov. 2008 [Online]. Available: http://www.amd.com/us-en/assets/contentty_pe/whitepapers_and_tech_docs/40546.pdf.
Sun Microsystems Inc.: UltraSPARC T2 processor. Sun Microsystems Data Sheets, 2007, [Online] Available: http://www.sun.com/processors/UltraSPARCT2/datasheet.pdf.
Johnson, T., Nawathe, U.: An 8-core, 64-thread, 64-bit power efficient SPARC SoC (niagara2). In Proceedings of 2007 International Symposium on Physical Design (ISPD ’07), pp. 2–2, ACM, (2007).
ARM Ltd.: The ARM Cortex-A9 Processors. ARM Ltd. White Paper, Sept. 2007 [Online] Available: http://www.arm.com/pdfs/ARMCortexA-9Processors.pdf.
NVIDIA Corp.: NVIDIA CUDA: Compute unified device architecture. NVidia CUDA Documentation, June2008. [Online] Available: http://developer.download.nvidia.com/compute/cuda/2_0/docs/NVIDIA_CUDA_Programming_Guide_2.0.pdf.
Zhuravlev, S., Saez, J.C., Blagodurov, S., Fedorova, A., Prieto, M.: Survey of Energy- Cognizant Scheduling Techniques, vol. 24(7); pp. 1447–1464, IEEE (2013).
David Chinnery, Kurt Keutzer.: Overview of the Factors Affecting the Power Consumption. In proceeding of Tools and Techniques for Low Power Design, pp. 11–53, Springer, (2007).
Dennard, R.H., Gaensslen, F. H., Yu, H., Rideout, V.L., Bassous,E., LeBlanc, A.R.: Design of ion-implanted MOSFET’s with very small physical dimensions. In proceedings of IEEE Solid-State Circuits, vol. 12(1); pp. 38–50, IEEE (2007).
Hennessy, J.L., Pattersson, D.A.: Computer Architecture - A Quantitative Approach. Morgan Kaufmann, second edition (1996).
Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, Doug Burger.: Dark silicon and the end of multicore scaling. In proceeding of 38th International Symposium on Computer Architecture (ISCA), pp. 365–376, IEEE (2011).
Puttaswamy, K., Loh.: Thermal Herding: Microarchitecture Techniques for controlling hotspots in high-performance 3D integrated processors. In proceeding of 13th International Symposium on High Performance Computer Architecture, pp. 193–204, IEEE (2007).
Fazal Hameed, Mohammad Abdullah Al Faruque, Jorg Henkel.: Dynamic thermal management in 3D multi-core architecture through run-time adaptation. In proceeding of Design, Automation & Test in Europe Conference & Exhibition, pp. 1–6, IEEE (2011).
Kontorinis, V., Shayan, A., Tullsen, D., Kumar, R.: Reducing Peak Power with a Table-Driven Adaptive Processor Core. In Proceedings of IEEE/ACM 42nd Annual International Symposium on Microarchitecture (MICRO-42), pp. 189–200, IEEE (2009).
Rodrigues, R., Annamalai, A., Koren, I., Kundu, S., Khan, O.: Performance per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. In Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pp. 121–130, ACM (2011).
Narayanan, S., Sartori, J., Kumar, R., Jones, D.: Scalable Stochastic Processors. In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 335–338, IEEE (2010).
Kornaros G.: Multi-core Embedded Systems. Taylor and Francis Group, CRC Press, (2010).
Flautner, K., Kim, N., Martin, S., Blaauw, D., Mudge, T.: Drowsy Caches: Simple Techniques for Reducing Leakage Power. In Proceedings of 29th Annual International Symposium on Computer Architecture, pp. 148–157, IEEE (2002).
Le Cai, Yung-Hsiang Lu.: Joint Power Management of Memory and Disk. In Proceedings of the conference on Design, Automation and Test in Europe, pp. 86–91, IEEE Computer Society (2005).
Rakesh Kumar, Victor Zyuban, Dean M. Tullsen.: Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In Proceedings of 32nd International Symposium on Computer Architecture (ISCA), pp. 408–419, IEEE (2005).
Donald, D., Martonosi, M.: Techniques for Multicore Thermal Management: Classification and New Exploration. In Proceedings of 33rd International symposium on Computer Architecture, pp. 78–88, IEEE (2006).
Isci, C., Buyuktosunoglu, A., C.-Y. Chen, Bose, P., Martonosi, M.: An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. In Proceedings of 39th Annual IEEE/ACM International Symposium on MICRO-39, pp. 347–358, IEEE (2006).
Hewlett-Packard, Intel, Microsoft, Phoenix Technologies, Toshiba: Advanced Configuration and Power Interface Specification, Revision 4.0a. April 2010, [Online]. Available: http://www.acpi.info/spec.html.
Bassett, P., Saint-Laurent M.: Energy efficient design techniques for a digital signal processor. In Proceedings of International Conference on IC Design & Technology, pp. 1–4, IEEE (2012).
Leverich, J., Monchiero, M., Talwar, V., Ranganathan, P.: Power management of data center workloads using per-core power gating. IEEE Computer Architecture Letters, vol. 8(2); pp. 48–51, IEEE (2009).
Young-Si Hwang, Ki-Seok Chung: Dynamic Power Management Technique for Multicore Based Embedded Mobile Devices. IEEE Transactions on Industrial Informatics, vol. 9(3); pp. 1601–1612 (2013).
Chaparro, P., Gonzalez, J., Magklis, G., Cai, Q. Gonzalez, A.: Understanding the Thermal Implications of Multicore Archtectures. IEEE Transactions on Parallel and Distributed Systems, vol.18 (8); pp. 1055–1065, IEEE (2007).
Hanumaiah, V., Vrudhula, S.: Energy-efficient Operation of Multicore Processors by DVFS, Task Migration and Active Cooling. Computers, vol. 63, no. 2, pp. 349–360, IEEE (2012).
B. de Abreu Silva, Bonato V.: Power/performance optimization in FPGA-based asymmetric multi-core systems. In Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 473–474, IEEE (2012).
Wonyoung Kim, Gupta M S, Gu-Yeon Wei, Brooks D.: System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of 14th International Symposium on High Performance Computer Architecture, pp. 123–134, IEEE (2008).
Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester.: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. In Proceedings of 4th International Symposium on Quality Electronic Design, pp. 287–292, IEEE (2003).
Burd, T., Pering, T., Stratakos, A., Brodersen, R.: A dynamic voltage scaled microprocessor system. In Proceedings of International Solid-State Circuits Conference, pp. 294–295, IEEE (2000).
Jayaseelan, R., Mitra, T.: A Hybrid Local-global Approach for Multi-core Thermal Management. In Proceedings of 2009 IEEE/ACM International Conference on Computer-Aided Design, pp. 314–320, IEEE (2009).
Pruhs, K., Van Stee, R., Uthaisombut, P.: Speed scaling of tasks with precedence constraints in approximation and online algorithms. In Proceedings of 3rd International conference on approximation and online algorithms, pp. 307–319, Springer (2006).
March, J.L., Sahuquillo, J., Hassan, H., Petit, S., Duato, J.: A new energy-aware dynamic task set partitioning algorithm for soft and hard embedded real-time systems. vol. 54, no. 8, pp. 1282–1294, The Computer Journal (2011).
Weiser, M., Welch, B., Demers, A., Shenker, S.: Scheduling for reduced CPU energy. In Proceedings of 1st USENIX conference on OSDI, pp. 13–23, ACM (1994).
Cai Qiong, Gonzalez, J., Magklis, G., Chaparro, P., Gonzalez, A.Q.:Thread shuffling: Combining DVFS and thread migration to reduce energy consumptions for multi-core systems. In Proceedings of 2011 International Symposium on Low Power Electronics and Design, pp. 379–384, IEEE (2011).
Quan Chen, Long Zheng, Minyi Guo, Zhiyi Huang.: EEWA: Energy-Efficient Workload-Aware Task Scheduling in Multi-core Architectures. In Proceedings of Parallel & Distributed Processing Symposium Workshops (IPDPSW), pp. 642–651, IEEE (2014).
Le Sueur E., Heiser G.: Dynamic voltage and frequency scaling: The laws of diminishing returns. In Proceedings of Hot Power'10: Workshop on Power aware computing and systems, pp. 1–8 (2010).
Awan, M.A, Petters, S.M.: Enhanced Race-To-Halt: A Leakage-Aware Energy Management Approach for Dynamic Priority Systems. In Proceedings of 23rd EUROMICRO Conference on Real-Time Systems (ECRTS), pp. 92–101, IEEE (2011).
Li Li, Ken Choi, Haiqing Nan.: Activity-driven fine-grained clock gating and run time power gating integration, vol. 21(8); pp. 1540–1544, IEEE (2013).
Hai Li, Swarup Bhunia, Yiran Chen, Vijaykumar T N, Roy K.: Deterministic Clock Gating for Microprocessor Power Reduction. In Proceedings of 9th International Symposium on High-Performance Computer Architecture, pp. 113–122, IEEE (2003).
Zhigang Hu, Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson Bose, P.: Micro architectural Techniques for Power Gating of Execution Units. In Proceedings of 2004 International Symposium on Low Power Electronics and Design, pp. 32–37, IEEE (2004).
Lungu, A., Bose, P., Buyuktosunoglu, A., Sorin, D.: Dynamic Power Gating with Quality Guarantees. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 377–382, IEEE (2009).
Rajesh Kumar, Glenn Hinton.: A Family of 45 nm IA Processors. In Proceedings of IEEE International Solid-State Circuits Conference, pp. 58–59, IEEE (2009).
Lloyd Bircher, Lizy, W., John, K.: Analysis of Dynamic Power Management on Multi-Core Processors. In Proceedings of 22nd Annual International Conference on Supercomputing, pp. 327–338, ACM (2008).
Dan Nicolaescu, Alex Veidenbaum, Alex Nicolau: Reducing Data Cache Energy Consumption via Cached Load/Store Queue. In Proceedings of 2003 International Symposium on Low Power Electronics and Design, pp. 252–257, IEEE (2003).
Carazo, P., Apolloni, R., Castro, F., Chaver, D., Pinuel, L., Tirado F.: L1 Data cache power reduction using a forwarding predictor, vol. 6448; pp. 116–125, Springer (2011).
Hsin-Hao Chu, Yu-Chon Kao, Ya-Shu Chen.: Adaptive thermal-aware task scheduling for multi-core systems. vol. 99; pp. 155–174, ELSEVIER (2015).
Heo, S., Barr, K., Asanovi, K.: Reducing power density through activity migration. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design, pp. 217–222, IEEE (2003).
Wu, G., Xu, Z., Xia, Q., Ren, J., Xia, F.: Task allocation and migration algorithm for temperature-constrained real-time multi-core systems. In Proceedings of 2010 IEEE/ACM International Conference on Green Computing and Communications, pp. 189–196, IEEE (2010).
Carpenter, J., Funk, S., Holman, P., Srinivasan, A., Anderson, J., Baruah, S.: A Categorization of Real-time Multiprocessor Scheduling Problems and Algorithms. In Handbook on Scheduling Algorithms, Methods, and Models, pp. 30.1–30.19 (2006).
Andersson, B.: Global Static-Priority Preemptive Multiprocessor Scheduling with Utilization Bound 38%. In Proceedings of ACM International Conference on Principles of Distributed Systems (OPODIS), vol. 5401; pp. 73–88, ACM (2008).
Andersson, B., Baruah, S., Jonsson, J.: Static-Priority Scheduling on Multiprocessors. In Proceedings of 2nd Real-Time Systems Symposium, pp. 193–202, IEEE (2001).
Kato, S., Yamasaki, N.: Semi-partitioned fixed-priority scheduling on multiprocessors. In Proceedings of 15th Real-Time and Embedded Technology and Applications Symposium, pp. 23–32, IEEE (2009).
Andersson, B., Bletsas, K, Baruah, S.: Scheduling Arbitrary Deadline Sporadic Task Systems on Multiprocessors. In Proceedings of Real-Time Systems Symposium, pp. 385–394, IEEE (2008).
Lundberg, L.: Analyzing fixed-priority global multiprocessor scheduling. In Proceedings of 8th Real-Time and Embedded Technology Symposium, pp. 145–153, IEEE (2002).
Baker, T.P.: An analysis of EDF schedulability on a multiprocessor. vol. 18(8); pp. 760–768, IEEE (2005).
Baruah, S.K, Shun-Shii Lin: Pfair scheduling of generalized pinwheel task systems. Transactions on Computers, vol.47 (7); pp. 812–816, IEEE (1998).
Fisher, N., J.-J. Chen, Wang, S. Thiele, L.: Thermal aware global real-time scheduling on multicore systems. In Proceedings of Real-Time and Embedded Technology and Applications Symposium, pp. 131–140, IEEE (2009).
Wang, S., Bettati, R.: Delay analysis in temperature constrained hard real-time systems with general task arrivals. In Proceedings of 27th IEEE International Real-Time Systems Symposium, pp. 323–334, IEEE (2006).
Levin, G., Funk, S., Sadowski, C., Pye, I., Brandt, S.: DP-fair: A simple model for understanding optimal multiprocessor scheduling. In Proceedings of 22nd EUROMICRO Conference, pp. 313, IEEE (2010).
Ming Fan, Qiushi Han, Gang Quan, Shangping Ren: Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBound. In Proceedings of 15th International Symposium on Quality Electronic Design, pp. 284–291, IEEE (2014).
Ming Fan, Qiushi Han, Shuo Liu, Shaolei Ren, Gang Quan, Shangping Ren: Enhanced fixed-priority real-time scheduling on multi-core platforms by exploiting task period relationship. pp. 85–96, Elsevier (2014).
Liu, J.W.S.: Real-time systems. Prentice Hall (2000).
Andersson, B., Jonsson, J.: The utilization bounds of partitioned and pfair static priority scheduling on multiprocessors are 50%. In Proceedings of 15th EUROMICRO Conference on Real-time Systems, pp. 33–40, IEEE (2003).
Guan, N., Martin Stigge, Wang Yi, Ge Yu: Parametric Utilization Bounds for Fixed-Priority Multiprocessor Scheduling. In Proceedings of 26th International Parallel and Distributed Processing Symposium, pp. 261–272, IEEE (2012).
Anderson, J.H., Bud, V., Devi, U.C.: An EDF-Based Scheduling Algorithm for Multiprocessor Soft Real-Time Systems. In Proceedings of EUROMICRO Conference on Real-Time Systems (ECRTS), pp. 199–208, IEEE (2005).
Bastoni, A., Brandenburg, B.B, Anderson, J.H.: Is Semi-partitioned scheduling practical? In Proceedings of 23rd Conference on Real-Time Systems, pp. 125–135, IEEE, (2011).
Kato, S., Yamasaki, N.: Semi-partitioned fixed-priority scheduling on multiprocessors. In Proceedings of 15th Real-Time and Embedded Technology and Applications Symposium, pp. 23–32, IEEE (2009).
Lakshmanan, K., Rajkumar, R., Lehoczky, J.P.: Partitioned fixed priority preemptive scheduling for multi-core processors. In Proceedings of 21st EUROMICRO Conference on Real-Time Systems, pp. 239–248, IEEE (2009).
Guan, N., Stigge, M., Yi, W., Yu G.: Fixed-Priority Multiprocessor Scheduling with Liu and Layland’s Utilization Bound. In Proceedings of IEEE Real Time and Embedded Technology and Applications Symposium (RTAS), pp. 165–174, IEEE (2010).
Guan, N., Martin Stigge, Wang Yi, Ge Yu: Fixed-Priority Multiprocessor Scheduling: Beyond Liu and Layland’s Utilization Bound. In Proceedings of WiP Real-Time Systems Symposium (RTSS), pp. 1594–1601, IEEE, (2010).
Zhang, Y., Guan, N., Yi. W.: Towards the Implementation and Evaluation of Semi-Partitioned Multi-Core Scheduling. In Bringing Theory to Practice: Predictability and Performance in Embedded Systems. vol. 18; pp. 42–46, In Open Access Series in Informatics (2011).
Gomaa, M., Powell, M.D., Vijaykumar, T. N.: Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. In Proceedings of ASPLOS, vol. 38(5); pp. 260–270, ACM (2004).
Pierre Michaud, Andre Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou: A study of thread migration in temperature constrained multicores. vol. 4(2); Article No. 9, ACM (2007).
Swaminathan, V., Chakrabarty, K.: Real-time task scheduling for energy-aware embedded systems. Journal of the Franklin Institute, vol. 338, pp. 729–750 (2001).
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Nagalakshmi, K., Gomathi, N. (2017). Analysis of Power Management Techniques in Multicore Processors. In: Dash, S., Vijayakumar, K., Panigrahi, B., Das, S. (eds) Artificial Intelligence and Evolutionary Computations in Engineering Systems. Advances in Intelligent Systems and Computing, vol 517. Springer, Singapore. https://doi.org/10.1007/978-981-10-3174-8_35
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