Abstract
The aim of the paper is to design evolvable hardware (EHW) architecture for Finite Impulse Response Filter using Genetic Algorithm. Evolvable hardware refers to hardware that can change its behaviour (parameters such as coefficients) according to the changes in its environment. To update the filter coefficients adaptively, genetic algorithm was used. The proposed filter architecture was implemented with Xilinx Spartan 6 FPGA (XC6SLX45-CSG324) Trainer Kit. Hardware design was synthesized using the EDK (Embedded Development Kit) platform and the genetic algorithm was implemented in SDK (Software Development Kit) of Xilinx Platform Studio tool (XPS) 14.6.
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Krishnaveni, K., Ranjith, C., Joy Vasantha Rani, S.P. (2017). Evolvable Hardware Architecture Using Genetic Algorithm for Distributed Arithmetic FIR Filter. In: Dash, S., Vijayakumar, K., Panigrahi, B., Das, S. (eds) Artificial Intelligence and Evolutionary Computations in Engineering Systems. Advances in Intelligent Systems and Computing, vol 517. Springer, Singapore. https://doi.org/10.1007/978-981-10-3174-8_26
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DOI: https://doi.org/10.1007/978-981-10-3174-8_26
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