Abstract
With the development of the CMOS process, beyond 3 billion of transistors are integrated on chip. But the increasing power density becomes a serious problem making the performance improvement slow down. Therefore, how to optimize the power consumption of multi-core processor is a crisis in processor design. This paper proposes a dual-threshold adaptive DVFS algorithm to dynamically control the processor voltage and frequency. Comparing with traditional single-threshold algorithm, experimental results show that dual-threshold adaptive DVFS can save more power with no obviously performance reduction. The performance of most benchmarks is beyond 90% of the original performance, while the power optimization can be up to 35%.
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References
Wall, D.W.: Limits of instruction-level parallelism. ACM SIGARCH Comput. Archit. News 26(4), 176–188 (1991)
Agerwala, T., Chatterjee, S.: Computer architecture: challenges and opportunities for the next decade. IEEE Micro 25(3), 58–69 (2005)
Teodorescu, R., Torrellas, J.: Variation-aware application scheduling and power management for chip multiprocessors. ACM SIGARCH Comput. Archit. News 36(3), 363–374 (2008). IEEE Computer Society
Lee, C., Lee, J.K., Hwang, T., et al.: Compiler optimization on VLIW instruction scheduling for low power. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 8(2), 252–268 (2003)
Pangjun, J., Sapatnekar, S.S.: Low-power clock distribution using multiple voltages and reduced swings. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10(3), 309–318 (2002)
Yi, H., Yang, X.: Optimizing the configuration of dynamic voltage scaling points in real-time applications. In: Paliouras, V., Vounckx, J., Verkest, D. (eds.) PATMOS 2005. LNCS, vol. 3728, pp. 79–88. Springer, Heidelberg (2005). doi:10.1007/11556930_9
Brooks, D., Martonosi, M.: Dynamic thermal management for high-performance microprocessors. In: Proceedings of PCA-7, pp. 171–82, January 2001
Pouwelse, J., Langendoen, K., Sips, H.: Dynamic voltage scaling on a low-power microprocessor. In: Proceedings of the 7th Annual International Conference on Mobile Computing and Networking, pp. 251–259. ACM (2001)
Le Sueur, E., Heiser, G.: Dynamic voltage and frequency scaling: the laws of diminishing returns. In: Proceedings of the 2010 International Conference on Power Aware Computing and Systems, pp. 1–8. USENIX Association (2010)
Kimura, H., Sato, M., Imada, T., et al.: Runtime DVFS control with instrumented code in power-scalable cluster system. In: 2008 IEEE International Conference on Cluster Computing, pp. 354–359. IEEE (2008)
Ge, R., Feng, X., Cameron, K.W.: Performance-constrained distributed DVS scheduling for scientific applications on power-aware clusters. In: Proceedings of the 2005 ACM/IEEE conference on Supercomputing, p. 34. IEEE Computer Society (2005)
Kong, J., Choi, J., Choi, L., et al.: Low-cost application-aware DVFS for multi-core architecture. In: Third 2008 International Conference on Convergence and Hybrid Information Technology, pp. 106–111. IEEE Computer Society (2008)
Eyerman, S., Eeckhout, L.: A counter architecture for online DVFS profitability estimation. IEEE Trans. Comput. 59(11), 1576–1583 (2010)
Bircher, W.L., John, L.: Predictive power management for multi-core processors. In: Varbanescu, A.L., Molnos, A., Nieuwpoort, R. (eds.) ISCA 2010. LNCS, vol. 6161, pp. 243–255. Springer, Heidelberg (2011). doi:10.1007/978-3-642-24322-6_21
Wei, D., Fei, F.Q., Kun, H., et al.: VB-DVFS: a new algorithm for power efficiency of CMP with GALS. In: 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 297–300. IEEE (2010)
Cai, Q., González, J., Rakvic, R., et al.: Meeting points: using thread criticality to adapt multi-core hardware to parallel regions. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 240–249. ACM (2008)
Wu, Q., Martonosi, M., Clark, D.W., et al.: A dynamic compilation framework for controlling microprocessor energy and performance. In: Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 271–282. IEEE Computer Society (2005)
Chabloz, J.M., Hemani, A.: Distributed DVFS using rationally-related frequencies and discrete voltage levels. In: 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), pp. 247–252 (2010)
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Zhang, C., Wang, J., Zhang, M., Wu, X. (2016). A New DVFS Algorithm Design for Multi-core Processor Chip. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2016. Communications in Computer and Information Science, vol 666. Springer, Singapore. https://doi.org/10.1007/978-981-10-3159-5_5
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DOI: https://doi.org/10.1007/978-981-10-3159-5_5
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