Abstract
The tested performance of a microprocessor chip is more important than the predicted performance of it’s model. However, performance deviations are often introduced during the design stages. In order to identify and fix the performance defects, a hierarchical performance verification methodology is proposed. Parameter sensitive performance models and coverage driven stimulus are built at the unit-level. Implementation oriented performance calibration and RTL simulation based benchmarks are made at the core-level. Prototyping and counter-based performance analysis systems are built in the system level. An example is given to demonstrate the application and effectiveness of the proposed methodology.
This work is supported in part by National Natural Science Foundation of China under grants 61170045.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Noonburg, D.B., Shen, J.P.: A framework for statistical modeling of superscalar processor performance. In: Third International Symposium on High-Performance Computer Architecture, pp. 298–309. IEEE, (1997)
Karkhanis, T.S., Smith, J.E.: A first-order superscalar processor model. ACM SIGARCH Comput. Archit. News 32, 338 (2004)
Ma, K.: Microprocessor analytical model. Ph.D. thesis, University of Science and Technology of China (2007)
Wang, L., Wang, Y., Li, L., Gao, J., Dou, Q.: Utilizing colored petri nets for design space exploration of asynchronous microprocessors. In: International Workshop on Reachability Problems (RP 2014), Oxford (2014)
Austin, T., Larson, E., Ernst, D.: Simplescalar: an infrastructure for computer system modeling. IEEE Comput. 35, 59–67 (2002)
Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., et al.: The gem5 simulator. ACM SIGARCH Comput. Archit. News 39, 1–7 (2011)
Virtutech: Virtutech simics - a full system simulator (2004)
Zhang, F.X., Zhang, L.B., Hu, W.W.: Sim-Godson: a Godson processor simulator based on simplescalar. Chin. J. Comput. 30, 68 (2007). Chinese Edition
Yi, J.J., Lilja, D.J.: Simulation of computer architectures: simulators, benchmarks, methodologies and recommendations. IEEE Trans. Comput. 55, 268–280 (2006)
John, L.K., Eeckhout, L. (eds.): Performance Evaluation and Benchmarking. CRC Press, New York (2006)
Black, B., Shen, J.P.: Calibration of microprocessor performance models. Computer 31, 59–65 (1998)
Desikan, R., Burger, D., Keckler, S.W.: Measuring experimental error in microprocessor simulation. In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, pp. 266–277. ACM, New York (2001)
John, L.K.: Benchmarks. In: Performance Evaluation and Benchmarking. CRC Press, pp. 27–44 (2006)
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 3rd edn. Morgan Kaufmann Publisher, San Francisco (2002)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Wang, Y., Huang, L., Zheng, Z. (2016). A Methodology for Performance Verification of Microprocessors. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2016. Communications in Computer and Information Science, vol 666. Springer, Singapore. https://doi.org/10.1007/978-981-10-3159-5_3
Download citation
DOI: https://doi.org/10.1007/978-981-10-3159-5_3
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-3158-8
Online ISBN: 978-981-10-3159-5
eBook Packages: Computer ScienceComputer Science (R0)
