Abstract
The performance of the adder entirely influenced by the performance of its basic modules. In this paper, a new hybrid 1-bit 14 transistor full adder design is proposed. The proposed circuit has been implemented using pass gate as well as CMOS logic hence named hybrid. The main design objective for this circuit is low power consumption and full voltage swing at a low supply voltage. As a result the proposed adder cell remarkably improves the power consumption, power-delay product and has less parasitic capacitance when compared to the 16T design. It also improves layout area by 7–8 % than its peer design. All simulations are performed at 90 & 45 nm process technology on Synopsys tool.
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References
N. Weste, K. Eshraghian, Principles of CMOS Digital Design. A System Perspective (Addison Wesley, Massachusetts, MA, USA, 1993)
S. Kang, Y. Leblebici, CMOS Digital Integrated Circuit Analysis and Design, 3rd edn. (McGraw-Hill, 2005)
K. Roy, S.C. Prasad, Low Power CMOS VLSI Circuit Design. ISBN 0471-11488 (2000)
R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits 32(7), 1079–1090 (1997)
D. Radhakrishnan, Low-voltage low-power CMOS full adder. IEEE Proc. Circuits Devices Syst. 148(1), 19–24 (2001)
A.M. Shams, T.K. Darwish, M. Bayoumi, Performance analysis of low-power1-bit CMOS full adder cells. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10(1), 20–29 (2002)
H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of low power 10-transistor full adders using novel XOR-XNOR gates. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 49(1), 25–30 (2002)
M. Zhang, J. Gu, C.-H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in Proceedings of the International Symposium on Circuits and Systems, pp. 317–320 (2003)
C.H. Chang, J.M. Gu, M. Zhang, A review of 0.18-μm full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13(6), 686–695 (2005)
S.R. Chowdhury, A. Banerjee, A. Roy, H. Saha, A high speed 8 transistor full adder design using novel 3 transistor XOR gates. Int. J. Electron. Circuits Syst. 2, 217–223 (2008)
A. Bazzazi, B. Eskafi, Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18 μm CMOS Technology, in Proceedings of the International Multiconference of Engineers and Computer Scientist, vol. II, IMECS Hong Kong (2010)
S. Goel, A. Kumar, M. Bayoumi, Design of robust, energy-efficient full adders for deep-sub micrometer design using hybrid-CMOS logic style, in IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(12), 130–1320 (2006)
M. Aguirre-Hernandez, M. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications, in Proceedings of the 4th IEEE VLSI Systems, vol. 19, pp. 718–721(2011)
B. Sathiyabama, Dr. S. Malarkkan, Novel low power hybrid adders using 90 nm technology for DSP applications. 1(2) (2012). ISSN:2278–067X
C.-K. Tung, S.-H. Shieh, C.-H. Cheng, Low-power high-speed full adder for portable electronic applications. Electron. Lett. 49 (2013)
P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. 10th IEEE Trans. Very Large Scale Integr. Syst. 23 (2015)
I.M. Filanovsky, A. Allam, Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans Circuits Syst. I: Fund. Theory Appl., 876–884 (2001)
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Sugandha, C., Tripti, S. (2017). Low Power 14T Hybrid Full Adder Cell. In: Satapathy, S., Bhateja, V., Udgata, S., Pattnaik, P. (eds) Proceedings of the 5th International Conference on Frontiers in Intelligent Computing: Theory and Applications . Advances in Intelligent Systems and Computing, vol 516. Springer, Singapore. https://doi.org/10.1007/978-981-10-3156-4_15
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DOI: https://doi.org/10.1007/978-981-10-3156-4_15
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