Abstract
In 1965, Gordon Moore proposed the rule that the number of devices on the wafer would be doubled every 18–24 months. This “Moore’s law” describes the continuous and rapid trend of scaling. Every reduction of feature size will be called a technology generation or technology node. The technology nodes include 0.18, 0.13, 90, 65, and 45 μm.
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Wu, YC., Jhan, YR. (2018). 3D FinFET with L g = 15 nm and L g = 10 nm Simulation. In: 3D TCAD Simulation for CMOS Nanoeletronic Devices. Springer, Singapore. https://doi.org/10.1007/978-981-10-3066-6_3
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DOI: https://doi.org/10.1007/978-981-10-3066-6_3
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