Abstract
The research article discusses the flow of product design helpful for semiconductor design companies. Chip-manufacturing industries are fabricating next-generation 3D IC and their packaging is the new challenge. The 3D packaging has low power dissipation, high density, high performance, and reliability. Microelectronics industries follow the 3D IC development based on the TSV technology, processing of micro-bumps, helpful for interconnecting the stacking chips. The reliability of 3D IC, using TSV interposer, is reviewed in detail for Xilinx FPGA environment. The flow and process of WoW stacking methodology followed by low temperature for TSV fabrication are also discussed. 3D interconnection technologies possess excellent reliability and applied for 3D integration in real-time applications and manufacturing. Cost, supply chains, and heat management are the challenges in 3D integration, and chip-package interaction (CPI) is also the reliability issue of 3D IC integration. To reduce the CPI, differential heating/cooling (H/C) chip-joining technique is also discussed, which effectively reduce fractures in ultra-low–k (ULK) Si chips.
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Banijamali B, Ramalingam S, Nagarajan K, Chaware R (2011) Advanced reliability study of TSV interposers and interconnects for the 28 nm technology FPGA. In: Proceedings of Electronic components and technology conference (ECTC)
Kitada H, Maeda N, Fujimoto K, Mizushima Y, Nakata Y, Nakamura T et al (2010) Stress and diffusion resistance of low temperature CVD dielectrics for multi- TSVs on bumpless wafer-on-wafer (WOW) technology. In: Advanced metallization conference
Fujimoto K et al (2010) Development of multi-stack process on wafer-on-wafer (WoW). In: The IEEE CPMT symposium Japan
Nimura M, Mizuno J, Shigetou A, Sakuma K, Ogino H, Enomoto T, Shoji S (2013) Study on hybrid Au–underfill resin bonding method with lock-and-key structure for 3-D integration. IEEE Trans Compon Packag Manuf Technol 3(4):558–565
Beyne E (2007) IMEC Kapeldreef 75,3001 Leuven “Tutorial T7A: Advanced IC packaging”. In: 20th International Conference on VLSI Design (VLSID’07), 2007, p 1
Fukushima T, Iwata E, Ohara Y, Murugesan M, Bea J-C, Lee K-W, Tanaka T, Koyanagi M (2012) IEEE Trans Electron Devices 59:2956 (PDF by Alliva TSV and interposer technologies at Alliva, 2010, p 11)
Huang NKH, Jiang LJ, Yu H, Li J, Xu S, Ren H (2012) Fundamental components of the IC packaging electromagnetic interference (EMI) analysis. IEEE 141–144
Ito Y, Fukushima T, Lee K-W, Choki K, Tanaka T, Koyanagi M (2012) Flux-assisted self-assembly with microbump bonding for 3D heterogeneous integration. In: 2013 Electronic Components & Technology Conference, IEEE, pp 891–897
AbouGabol M (2011) Importance of integrated circuit (IC) packaging in semiconductor Companies design flow. In: IEEE GCC conference and Exhibition (GCC), Feb 2011 Dubai, United Arab Emirates, pp 355–356
Ko CT, Chen KN (2012) Reliability of key technologies in 3D integration. In: Microelectronics reliability, Elsevier, pp 7–12
Chen W-H, Yu C-F, Cheng HC, Tsai Y, Lu S-T (2012) IMC growth reaction and its effects on solder joint thermal cycling reliability of 3D chip stacking packaging. In: Microelectronics reliability. Elsevier, pp 30–40
Tu KN, Hsiao HY, Chen C (2012) Transition from flip chip solder joint to 3D IC micro bump: its effect on microstructure anisotropy. Elsevier, pp 2–6
Sakuma K, Smith K, Tunga K, Perfecto E, Wassick T, Pompeo F, Nah J-W (2012) Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k Technology. 978-1-4673-1965-2/12/$31.00 ©2012 IEEE, pp 430–436
Ohara Y, Noriki A, Sakuma AK, Lee K-W, Murugesan M, Bea J-C, Yamada F, Fukushima T, Tanaka T, Koyanagi M (2009) Proceedings of 3D System Integration, p 389
www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html
Lee Y-J, Su Y-F, Hung T-Y, Chiang K-N {2012) Reliability analysis of 3D IC integration packaging under drop test condition. IEEE Catalog Number: CFP1259B-ART, pp 299–302
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Kumar, A., Verma, G., Nath, V., Choudhury, S. (2017). IC Packaging: 3D IC Technology and Methods. In: Nath, V. (eds) Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems. Lecture Notes in Electrical Engineering, vol 403. Springer, Singapore. https://doi.org/10.1007/978-981-10-2999-8_25
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DOI: https://doi.org/10.1007/978-981-10-2999-8_25
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