Abstract
New charge pump with 130-nm technology with better efficiency is designed using complimentary MOSFET (CMOS) technique. To match the output voltage range with current of the charge pump, a current mirror with self-biasing has been introduced. This is not the exact procedure to remove perfect current mismatching, but it is one of the better ways to attain desired characteristics from the proposed charge pump design. On analysis, it is found that proposed design requires an average power of 0.01013 mW under locked condition when it is operated under 1-V power supply.
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Kumar, A., Paliwal, A.K., Sharma, S. (2017). Blueprint of a CMOS Charge Pump for Phase-Locked Loop Synthesizers with High Efficiency. In: Nath, V. (eds) Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems. Lecture Notes in Electrical Engineering, vol 403. Springer, Singapore. https://doi.org/10.1007/978-981-10-2999-8_20
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DOI: https://doi.org/10.1007/978-981-10-2999-8_20
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