Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power

  • T. S. Gokkul Nath
  • E. R. MidhilaEmail author
  • Ashwin Swaminathan
  • Binitaa Lekshmi
  • J. P. Anita
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 625)


As the manufacturing processes become more and more advanced as per Moore’s law, precise control of silicon process is becoming more and more challenging. This increases the probability of defects and has brought a necessity for testing to ensure fault-free products, making the testing of a chip more complex causing testing challenges.

With large number of transistors, in multiples of thousands being integrated in one chip, multiple stuck-at faults may exist, because of which fault masking and reinforcing effects may come into effect. This may lead to the failure of approaches like Single Location at a Time (SLAT) and restricted single sensitized paths. To counter this, the notion of fault element is used to take into account multiple fault models and use a fault element graph (FEG) to consider fault masking and reinforcing effects among multiple faults. To identify these faults, appropriate test patterns need to be generated that would carry the effect of the fault to the primary output. The test patterns are chosen such that switching power is made to be a minimum.


Fault Fault element graph Fault location Test pattern Failing pattern Switching power 


  1. 1.
    Jha, N., Gupta, S.: Testing of Digital Systems. Cambridge University Press, Cambridge (2003)CrossRefGoogle Scholar
  2. 2.
    Aitken, R.C.: Modeling the unmodelable: algorithmic fault diagnosis. IEEE Des. Test Comput. 14(3), 98–103 (1997)CrossRefGoogle Scholar
  3. 3.
    Huisman, L.M.: Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 23(1), 91–101 (2004)CrossRefGoogle Scholar
  4. 4.
    Lin, Y.C., Lu, F., Cheng, K.-T.: Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 26(5), 932–942 (2007)CrossRefGoogle Scholar
  5. 5.
    Lavo, D., Hartanto, I., Larrabee, T.: Multiplets, models, and the search for meaning: improving per-test fault diagnosis. In: Proceedings of International Test Conference, pp. 250–259, January 2002Google Scholar
  6. 6.
    Wang, Z., Tsai, K.-H., Kun-Han, T., Marek-Sadowska, M., Rajski, J.: An efficient and effective methodology on the multiple fault diagnosis. In: Proceedings of International Test Conference, pp. 329–338, October 2003Google Scholar
  7. 7.
    Wang, Z., Marek-Sadovvska, M., Kun-Han, T., Rajski, J.: Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 25(3), 558–575 (2006)CrossRefGoogle Scholar
  8. 8.
    Yu, X., Blanton, R.D.: Multiple defect diagnosis using no assumptions on failing pattern characteristics. In: Proceedings of 45th ACM/IEEE Design Automation Conference, pp. 361–366, June 2008Google Scholar
  9. 9.
    Yu, X., Blanton, R.D.: Diagnosis of integrated circuits with multiple defects of arbitrary characteristics. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 29(6), 977–987 (2010)CrossRefGoogle Scholar
  10. 10.
    Veneris, A., Liu, J., Amiri, M., Abadir, M.S.: Incremental diagnosis and correction of multiple faults and errors. In: Proceedings of Design Automation Test European Conference and Exhibition, pp. 716–721, March 2002Google Scholar
  11. 11.
    Smith, A., Veneris, A., Viglas, A.: Design diagnosis using Boolean satisfiability. In: Proceedings Asian South Pacific Design Automation Conference, pp. 218–223, January 2004Google Scholar
  12. 12.
    Takahashi, H., Boateng, K.O., Saluja, K.K., Takamatsu, Y.: On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 21(3), 362–368 (2002)CrossRefGoogle Scholar
  13. 13.
    Hu, Y., Li, X., Cheng, W., Huang, Y., Tang, H.: Diagnose failures caused by multiple locations at a time. IEEE Trans. VLSI 22(4), 824–837 (2014)CrossRefGoogle Scholar
  14. 14.
    Mohan, N., Anita, J.P.: A zero suppressed binary decision diagram based test set relaxation for single and multiple stuck-at faults. Int. J. Math. Model. Numer. Optim. 7(1), 83–96 (2016)Google Scholar
  15. 15.
    Sinduja, V., Raghav, S., Anita, J.P.: Efficient don’t-care filling method to achieve reduction in test power. In: Proceedings of International Test Conference, Advances in Computing, Communications and Informatics, pp. 478–482, August 2015Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2016

Authors and Affiliations

  • T. S. Gokkul Nath
    • 1
  • E. R. Midhila
    • 1
    Email author
  • Ashwin Swaminathan
    • 1
  • Binitaa Lekshmi
    • 1
  • J. P. Anita
    • 1
  1. 1.ChennaiIndia

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