Magnetic Domain Wall Race Track Memory

  • Brajesh Kumar KaushikEmail author
  • Shivam Verma
  • Anant Aravind Kulkarni
  • Sanjay Prajapati
Part of the SpringerBriefs in Applied Sciences and Technology book series (BRIEFSAPPLSCIENCES)


During the past four decades, semiconductor industry has witnessed a race between the development of processing devices/systems and memory technologies following the Moore’s law. With the end of Moore’s era on the silicon roadmap, the processing technologies are apparent frontrunner than the memory counterparts in terms of accessing speed and integration volumes.


Domain Wall Magnetic Domain Flash Memory Domain Wall Motion Memory Hierarchy 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    X. Fong, S. H. Choday, and K. Roy. More than Moore technologies for next generation computer design. Springer, NY USA, 2015. Ch. 6.Google Scholar
  2. 2.
    A. Makarov, V. Sverdlov, and S. Selberherr, “Emerging memory technologies: Trends, challenges, and modeling methods,” Microelect. Reliab., vol. 52, no. 4, pp. 628–634, 2012.Google Scholar
  3. 3.
    H.-S. P. Wong and S. Salahuddin, “Memory leads the way to better computing,” Nat. Nanotech., vol. 10, pp. 191–194, 2015.Google Scholar
  4. 4.
    H. Li, Y. Chen, Nonvolatile memory design, magnetic, resistive and phase change, CRC Press, NY USA, 2012, Ch. 1.Google Scholar
  5. 5.
    S. Verma, S. Kaundal, and B. K. Kaushik, “Novel 4F 2 buried-source-line STT MRAM cell with vertical GAA transistor as select device,” IEEE Trans. Nanotech., vol. 13, no. 6, pp. 1163–1171, 2014.Google Scholar
  6. 6.
    L. Thomas, S.-H. Yang, K.-S. Ryu, B. Hughes, C. Rettner, D.-S. Wang, C.-H. Tsai, K.-H. Shen, and S. S. P. Parkin, “Racetrack Memory: A high-performance, low-cost, non-volatile memory based on magnetic domain walls,” Elect. Dev. Meet. (IEDM), 2011 IEEE Int., pp. 24–24.2.4, 2011.Google Scholar
  7. 7.
    Y. Zhang, W. Zhao, J. O. Klein, D. Ravelsona, and C. Chappert, “Ultra-high density content addressable memory based on current induced domain wall motion in magnetic track,” IEEE Trans. Mag., vol. 48, no. 11, pp. 3219–3222, 2012.Google Scholar
  8. 8.
    L. Berger, “Low-field magnetoresistance and domain drag in ferromagnets,” J. Appl. Phys., vol. 49, no. 3, pp. 2156–2161, 1978.Google Scholar
  9. 9.
    S. Fukami, M. Yamanouchi, S. Ikeda, and H. Ohno, “Domain wall motion device for nonvolatile memory and logic - size dependence of device properties,” IEEE Trans. Mag., vol. 50, no. 11, 2014.Google Scholar
  10. 10.
    Y. Zhang, W. S. Zhao, D. Ravelosona, J. O. Klein, J. V. Kim, and C. Chappert, “Perpendicular-magnetic-anisotropy CoFeB racetrack memory,” J. Appl. Phys., vol. 111, no. 9, 2012.Google Scholar
  11. 11.
    S. Parkin and S.-H. Yang, “Memory on the racetrack,” Nat. Nanotech., vol. 10, no. 3, pp. 195–198, 2015.Google Scholar
  12. 12.
    G. S. D. Beach, M. Tsoi, and J. L. Erskine, “Current-induced domain wall motion,” J. Magn. Mag. Mater., vol. 320, no. 7, pp. 1272–1281, 2008.Google Scholar
  13. 13.
    K. Kawabata, M. Tanizawa, K. Ishikawa, Y. Inoue, M. Inuishi, and T. Nishimura, “Study of current induced magnetic domain wall movement with extremely low energy consumption by micromagnetic simulation,” IEEE 2011 Int. Conf. Simul. Semicond. Proce. Dev., pp. 55–58, 2011.Google Scholar
  14. 14.
    S. Fukami, M. Yamanouchi, K. J. Kim, T. Suzuki, N. Sakimura, D. Chiba, S. Ikeda, T. Sugibayashi, N. Kasai, T. Ono, and H. Ohno, “20-Nm magnetic domain wall motion memory with ultralow-power operation,” IEEE Tech. Dig. - Int. Elect. Dev. Meet. IEDM, pp. 72–75, 2013.Google Scholar
  15. 15.
    G. Tatara, H. Kohno, and J. Shibata, “Microscopic approach to current-driven domain wall dynamics,” Phys. Rep., vol. 468, no. 6, pp. 213–301, 2008.Google Scholar
  16. 16.
    W. Zhao, D. Ravelosona, J. O. Klein, and C. Chappert, “Domain wall shift register-based reconfigurable logic,” IEEE Trans. Mag., vol. 47, no. 10, pp. 2966–2969, 2011.Google Scholar
  17. 17.
    A. Yamaguchi, S. Nasu, H. Tanigawa, T. Ono, K. Miyake, K. Mibu, and T. Shinjo, “Effect of Joule heating in current-driven domain wall motion,” Appl. Phys. Lett., vol. 86, no. 1, pp. 10–13, 2005.Google Scholar
  18. 18.
    K. Huang and R. Zhao, “Magnetic domain-wall racetrack memory-based nonvolatile logic for low-power computing and fast run-time-reconfiguration,” IEEE Trans. VLSI. Sys., vol. 24, no. 9, pp. 2861–2872, 2016.Google Scholar
  19. 19.
    H. Nakamura, S. Li, X. Liu, and A. Morisako, “Current-induced domain wall motion in TbFeCo micro wire with perpendicular magnetic anisotropy,” J. Phys. Conf. Ser., vol. 266, no. 6, p. 012082, 2011.Google Scholar
  20. 20.
    S. J. Noh, Y. Miyamoto, M. Okuda, N. Hayashi, and Y. Keun Kim, “Effects of notch shape on the magnetic domain wall motion in nanowires with in-plane or perpendicular magnetic anisotropy,” J. Appl. Phys., vol. 111, no. 7, pp. 2014–2017, 2012.Google Scholar
  21. 21.
    S. Fukami, T. Suzuki, K. Nagahara, N. Ohshima, Y. Ozaki, S. Saito, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, C. Igarashi, S. Miura, N. Ishiwata, and T. Sugibayashi, “Low-current perpendicular domain wall motion cell for scalable high-speed MRAM,” 2009 Symp. VLSI Tech. Dig. Tech. Pap., pp. 230–231, 2009.Google Scholar
  22. 22.
    S. S. P. Parkin, “Data in the fast lanes of racetrack memory,” Sci. Am., vol. 300, no. 6, pp. 76–81, 2009.Google Scholar
  23. 23.
    S. S. P. Parkin, M. Hayashi, and L. Thomas, “Magnetic domain wall racetrack memory,” Science, vol. 320, no. 5873, pp. 190–194, 2008.Google Scholar
  24. 24.
    A. J. Annunziata, M. C. Gaidis, L. Thomas, C. W. Chien, C. C. Hung, P. Chevalier, E. J. O’Sullivan, J. P. Hummel, E. A. Joseph, Y. Zhu, T. Topuria, E. Delenia, P. M. Rice, S. S. P. Parkin, and W. J. Gallagher, “Racetrack memory cell array with integrated magnetic tunnel junction readout,” IEEE Tech. Dig. - Int. Elect. Dev.Meet. IEDM, no. c, pp. 539–542, 2011.Google Scholar
  25. 25.
    H. P. Trinh, W. Zhao, J. O. Klein, Y. Zhang, D. Ravelsona, and C. Chappert, “Magnetic adder based on racetrack memory,” IEEE Trans. Cir. Sys.-I Regu. Pap., vol. 60, no. 6, pp. 1469–1477, 2013.Google Scholar

Copyright information

© The Author(s) 2017

Authors and Affiliations

  • Brajesh Kumar Kaushik
    • 1
    Email author
  • Shivam Verma
    • 1
  • Anant Aravind Kulkarni
    • 1
  • Sanjay Prajapati
    • 1
  1. 1.Department of Electronics and Communication EngineeringIndian Institute of Technology RoorkeeRoorkeeIndia

Personalised recommendations